2018-02-05 00:08:20 +01:00
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using ChocolArm64.Instruction;
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using ChocolArm64.State;
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namespace ChocolArm64.Decoder
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{
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class AOpCodeSimd : AOpCode, IAOpCodeSimd
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{
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public int Rd { get; private set; }
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public int Rn { get; private set; }
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public int Opc { get; private set; }
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public int Size { get; protected set; }
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2018-02-10 18:20:46 +01:00
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public AOpCodeSimd(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
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2018-02-05 00:08:20 +01:00
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{
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Rd = (OpCode >> 0) & 0x1f;
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Rn = (OpCode >> 5) & 0x1f;
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Opc = (OpCode >> 15) & 0x3;
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Size = (OpCode >> 22) & 0x3;
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RegisterSize = ((OpCode >> 30) & 1) != 0
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? ARegisterSize.SIMD128
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: ARegisterSize.SIMD64;
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}
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}
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}
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