Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
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#define AluBinary
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2020-07-13 12:48:14 +02:00
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using ARMeilleure.State;
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("AluBinary")]
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public sealed class CpuTestAluBinary : CpuTest
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{
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#if AluBinary
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2020-07-13 12:48:14 +02:00
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public struct CrcTest
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{
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public uint Crc;
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public ulong Value;
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public bool C;
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public uint[] Results; // One result for each CRC variant (8, 16, 32)
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public CrcTest(uint crc, ulong value, bool c, params uint[] results)
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{
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Crc = crc;
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Value = value;
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C = c;
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Results = results;
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}
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}
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#region "ValueSource (CRC32)"
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private static CrcTest[] _CRC32_Test_Values_()
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{
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// Created with http://www.sunshine2k.de/coding/javascript/crc/crc_js.html, with:
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// - non-reflected polynomials
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// - input reflected, result reflected
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// - bytes in order of increasing significance
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// - xor 0
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// Only includes non-C variant, as the other can be tested with unicorn.
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return new CrcTest[]
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{
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new CrcTest(0x00000000u, 0x00_00_00_00_00_00_00_00u, false, 0x00000000, 0x00000000, 0x00000000, 0x00000000),
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new CrcTest(0x00000000u, 0x7f_ff_ff_ff_ff_ff_ff_ffu, false, 0x2d02ef8d, 0xbe2612ff, 0xdebb20e3, 0xa9de8355),
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new CrcTest(0x00000000u, 0x80_00_00_00_00_00_00_00u, false, 0x00000000, 0x00000000, 0x00000000, 0xedb88320),
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new CrcTest(0x00000000u, 0xff_ff_ff_ff_ff_ff_ff_ffu, false, 0x2d02ef8d, 0xbe2612ff, 0xdebb20e3, 0x44660075),
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new CrcTest(0x00000000u, 0xa0_02_f1_ca_52_78_8c_1cu, false, 0x14015c4f, 0x02799256, 0x9063c9e5, 0x8816610a),
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new CrcTest(0xffffffffu, 0x00_00_00_00_00_00_00_00u, false, 0x2dfd1072, 0xbe26ed00, 0xdebb20e3, 0x9add2096),
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new CrcTest(0xffffffffu, 0x7f_ff_ff_ff_ff_ff_ff_ffu, false, 0x00ffffff, 0x0000ffff, 0x00000000, 0x3303a3c3),
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new CrcTest(0xffffffffu, 0x80_00_00_00_00_00_00_00u, false, 0x2dfd1072, 0xbe26ed00, 0xdebb20e3, 0x7765a3b6),
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new CrcTest(0xffffffffu, 0xff_ff_ff_ff_ff_ff_ff_ffu, false, 0x00ffffff, 0x0000ffff, 0x00000000, 0xdebb20e3),
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new CrcTest(0xffffffffu, 0xa0_02_f1_ca_52_78_8c_1cu, false, 0x39fc4c3d, 0xbc5f7f56, 0x4ed8e906, 0x12cb419c)
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};
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}
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#endregion
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|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
|
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private const int RndCnt = 2;
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2020-07-13 12:48:14 +02:00
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[Test, Combinatorial]
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public void Crc32_b_h_w_x([Values(0u)] uint rd,
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[Values(1u)] uint rn,
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[Values(2u)] uint rm,
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[Range(0u, 3u)] uint size,
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[ValueSource("_CRC32_Test_Values_")] CrcTest test)
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{
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uint opcode = 0x1AC04000; // CRC32B W0, W0, W0
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opcode |= size << 10;
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opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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if (size == 3)
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|
{
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opcode |= 0x80000000;
|
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|
}
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|
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|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
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SingleOpcode(opcode, x1: test.Crc, x2: test.Value, x31: w31, runUnicorn: false);
|
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|
|
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|
ExecutionContext context = GetContext();
|
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|
ulong result = context.GetX((int)rd);
|
|
|
|
Assert.That(result == test.Results[size]);
|
|
|
|
}
|
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
|
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|
[Test, Pairwise, Description("CRC32X <Wd>, <Wn>, <Xm>"), Ignore("Unicorn fails.")]
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public void Crc32x([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(2u, 31u)] uint rm,
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|
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
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[Values((ulong)0x00_00_00_00_00_00_00_00,
|
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|
(ulong)0x7F_FF_FF_FF_FF_FF_FF_FF,
|
|
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|
(ulong)0x80_00_00_00_00_00_00_00,
|
|
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(ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong xm)
|
|
|
|
{
|
|
|
|
uint opcode = 0x9AC04C00; // CRC32X W0, W0, X0
|
|
|
|
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
|
|
|
|
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
|
|
|
|
SingleOpcode(opcode, x1: wn, x2: xm, x31: w31);
|
|
|
|
|
|
|
|
CompareAgainstUnicorn();
|
|
|
|
}
|
|
|
|
|
|
|
|
[Test, Pairwise, Description("CRC32W <Wd>, <Wn>, <Wm>"), Ignore("Unicorn fails.")]
|
|
|
|
public void Crc32w([Values(0u, 31u)] uint rd,
|
|
|
|
[Values(1u, 31u)] uint rn,
|
|
|
|
[Values(2u, 31u)] uint rm,
|
|
|
|
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
|
|
|
[Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF,
|
|
|
|
(uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint wm)
|
|
|
|
{
|
|
|
|
uint opcode = 0x1AC04800; // CRC32W W0, W0, W0
|
|
|
|
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
|
|
|
|
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
|
|
|
|
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
|
|
|
|
|
|
|
CompareAgainstUnicorn();
|
|
|
|
}
|
|
|
|
|
|
|
|
[Test, Pairwise, Description("CRC32H <Wd>, <Wn>, <Wm>"), Ignore("Unicorn fails.")]
|
|
|
|
public void Crc32h([Values(0u, 31u)] uint rd,
|
|
|
|
[Values(1u, 31u)] uint rn,
|
|
|
|
[Values(2u, 31u)] uint rm,
|
|
|
|
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
|
|
|
[Values((ushort)0x00_00, (ushort)0x7F_FF,
|
|
|
|
(ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort wm)
|
|
|
|
{
|
|
|
|
uint opcode = 0x1AC04400; // CRC32H W0, W0, W0
|
|
|
|
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
|
|
|
|
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
|
|
|
|
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
|
|
|
|
|
|
|
CompareAgainstUnicorn();
|
|
|
|
}
|
|
|
|
|
|
|
|
[Test, Pairwise, Description("CRC32B <Wd>, <Wn>, <Wm>"), Ignore("Unicorn fails.")]
|
|
|
|
public void Crc32b([Values(0u, 31u)] uint rd,
|
|
|
|
[Values(1u, 31u)] uint rn,
|
|
|
|
[Values(2u, 31u)] uint rm,
|
|
|
|
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
|
|
|
[Values((byte)0x00, (byte)0x7F,
|
|
|
|
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm)
|
|
|
|
{
|
|
|
|
uint opcode = 0x1AC04000; // CRC32B W0, W0, W0
|
|
|
|
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
|
|
|
|
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
|
|
|
|
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
|
|
|
|
|
|
|
CompareAgainstUnicorn();
|
|
|
|
}
|
|
|
|
|
|
|
|
[Test, Pairwise, Description("CRC32CX <Wd>, <Wn>, <Xm>")]
|
|
|
|
public void Crc32cx([Values(0u, 31u)] uint rd,
|
|
|
|
[Values(1u, 31u)] uint rn,
|
|
|
|
[Values(2u, 31u)] uint rm,
|
|
|
|
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
|
|
|
[Values((ulong)0x00_00_00_00_00_00_00_00,
|
|
|
|
(ulong)0x7F_FF_FF_FF_FF_FF_FF_FF,
|
|
|
|
(ulong)0x80_00_00_00_00_00_00_00,
|
|
|
|
(ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong xm)
|
|
|
|
{
|
|
|
|
uint opcode = 0x9AC05C00; // CRC32CX W0, W0, X0
|
|
|
|
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
|
|
|
|
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
|
|
|
|
SingleOpcode(opcode, x1: wn, x2: xm, x31: w31);
|
|
|
|
|
|
|
|
CompareAgainstUnicorn();
|
|
|
|
}
|
|
|
|
|
|
|
|
[Test, Pairwise, Description("CRC32CW <Wd>, <Wn>, <Wm>")]
|
|
|
|
public void Crc32cw([Values(0u, 31u)] uint rd,
|
|
|
|
[Values(1u, 31u)] uint rn,
|
|
|
|
[Values(2u, 31u)] uint rm,
|
|
|
|
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
|
|
|
[Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF,
|
|
|
|
(uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint wm)
|
|
|
|
{
|
|
|
|
uint opcode = 0x1AC05800; // CRC32CW W0, W0, W0
|
|
|
|
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
|
|
|
|
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
|
|
|
|
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
|
|
|
|
|
|
|
CompareAgainstUnicorn();
|
|
|
|
}
|
|
|
|
|
|
|
|
[Test, Pairwise, Description("CRC32CH <Wd>, <Wn>, <Wm>")]
|
|
|
|
public void Crc32ch([Values(0u, 31u)] uint rd,
|
|
|
|
[Values(1u, 31u)] uint rn,
|
|
|
|
[Values(2u, 31u)] uint rm,
|
|
|
|
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
|
|
|
[Values((ushort)0x00_00, (ushort)0x7F_FF,
|
|
|
|
(ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort wm)
|
|
|
|
{
|
|
|
|
uint opcode = 0x1AC05400; // CRC32CH W0, W0, W0
|
|
|
|
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
|
|
|
|
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
|
|
|
|
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
|
|
|
|
|
|
|
CompareAgainstUnicorn();
|
|
|
|
}
|
|
|
|
|
|
|
|
[Test, Pairwise, Description("CRC32CB <Wd>, <Wn>, <Wm>")]
|
|
|
|
public void Crc32cb([Values(0u, 31u)] uint rd,
|
|
|
|
[Values(1u, 31u)] uint rn,
|
|
|
|
[Values(2u, 31u)] uint rm,
|
|
|
|
[Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
|
|
|
[Values((byte)0x00, (byte)0x7F,
|
|
|
|
(byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte wm)
|
|
|
|
{
|
|
|
|
uint opcode = 0x1AC05000; // CRC32CB W0, W0, W0
|
|
|
|
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
|
|
|
|
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
|
|
|
|
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
|
|
|
|
|
|
|
CompareAgainstUnicorn();
|
|
|
|
}
|
|
|
|
|
|
|
|
[Test, Pairwise, Description("SDIV <Xd>, <Xn>, <Xm>")]
|
|
|
|
public void Sdiv_64bit([Values(0u, 31u)] uint rd,
|
|
|
|
[Values(1u, 31u)] uint rn,
|
|
|
|
[Values(2u, 31u)] uint rm,
|
|
|
|
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
|
|
|
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
|
|
|
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
|
|
|
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
|
|
|
{
|
|
|
|
uint opcode = 0x9AC00C00; // SDIV X0, X0, X0
|
|
|
|
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
|
|
|
|
|
|
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
|
|
|
|
|
|
|
SingleOpcode(opcode, x1: xn, x2: xm, x31: x31);
|
|
|
|
|
|
|
|
CompareAgainstUnicorn();
|
|
|
|
}
|
|
|
|
|
|
|
|
[Test, Pairwise, Description("SDIV <Wd>, <Wn>, <Wm>")]
|
|
|
|
public void Sdiv_32bit([Values(0u, 31u)] uint rd,
|
|
|
|
[Values(1u, 31u)] uint rn,
|
|
|
|
[Values(2u, 31u)] uint rm,
|
|
|
|
[Values(0x00000000u, 0x7FFFFFFFu,
|
|
|
|
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
|
|
|
[Values(0x00000000u, 0x7FFFFFFFu,
|
|
|
|
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
|
|
|
{
|
|
|
|
uint opcode = 0x1AC00C00; // SDIV W0, W0, W0
|
|
|
|
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
|
|
|
|
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
|
|
|
|
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
|
|
|
|
|
|
|
CompareAgainstUnicorn();
|
|
|
|
}
|
|
|
|
|
|
|
|
[Test, Pairwise, Description("UDIV <Xd>, <Xn>, <Xm>")]
|
|
|
|
public void Udiv_64bit([Values(0u, 31u)] uint rd,
|
|
|
|
[Values(1u, 31u)] uint rn,
|
|
|
|
[Values(2u, 31u)] uint rm,
|
|
|
|
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
|
|
|
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
|
|
|
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
|
|
|
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm)
|
|
|
|
{
|
|
|
|
uint opcode = 0x9AC00800; // UDIV X0, X0, X0
|
|
|
|
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
|
|
|
|
|
|
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
|
|
|
|
|
|
|
SingleOpcode(opcode, x1: xn, x2: xm, x31: x31);
|
|
|
|
|
|
|
|
CompareAgainstUnicorn();
|
|
|
|
}
|
|
|
|
|
|
|
|
[Test, Pairwise, Description("UDIV <Wd>, <Wn>, <Wm>")]
|
|
|
|
public void Udiv_32bit([Values(0u, 31u)] uint rd,
|
|
|
|
[Values(1u, 31u)] uint rn,
|
|
|
|
[Values(2u, 31u)] uint rm,
|
|
|
|
[Values(0x00000000u, 0x7FFFFFFFu,
|
|
|
|
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
|
|
|
[Values(0x00000000u, 0x7FFFFFFFu,
|
|
|
|
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
|
|
|
|
{
|
|
|
|
uint opcode = 0x1AC00800; // UDIV W0, W0, W0
|
|
|
|
opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
|
|
|
|
|
|
|
|
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
|
|
|
|
|
|
|
SingleOpcode(opcode, x1: wn, x2: wm, x31: w31);
|
|
|
|
|
|
|
|
CompareAgainstUnicorn();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
}
|