2019-01-25 02:59:53 +01:00
|
|
|
using ChocolArm64.Decoders;
|
|
|
|
using ChocolArm64.State;
|
|
|
|
using ChocolArm64.Translation;
|
|
|
|
using System.Reflection.Emit;
|
|
|
|
|
|
|
|
using static ChocolArm64.Instructions.InstEmit32Helper;
|
|
|
|
using static ChocolArm64.Instructions.InstEmitAluHelper;
|
|
|
|
|
|
|
|
namespace ChocolArm64.Instructions
|
|
|
|
{
|
|
|
|
static partial class InstEmit32
|
|
|
|
{
|
|
|
|
public static void Add(ILEmitterCtx context)
|
|
|
|
{
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 17:06:11 +01:00
|
|
|
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
|
2019-01-25 02:59:53 +01:00
|
|
|
|
|
|
|
EmitAluLoadOpers(context, setCarry: false);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Add);
|
|
|
|
|
|
|
|
if (op.SetFlags)
|
|
|
|
{
|
|
|
|
context.EmitZnFlagCheck();
|
|
|
|
|
|
|
|
EmitAddsCCheck(context);
|
|
|
|
EmitAddsVCheck(context);
|
|
|
|
}
|
|
|
|
|
|
|
|
EmitAluStore(context);
|
|
|
|
}
|
|
|
|
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 17:06:11 +01:00
|
|
|
public static void Cmp(ILEmitterCtx context)
|
|
|
|
{
|
|
|
|
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
|
|
|
|
|
|
|
|
EmitAluLoadOpers(context, setCarry: false);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Sub);
|
|
|
|
|
|
|
|
context.EmitZnFlagCheck();
|
|
|
|
|
|
|
|
EmitSubsCCheck(context);
|
|
|
|
EmitSubsVCheck(context);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Pop);
|
|
|
|
}
|
|
|
|
|
2019-01-25 02:59:53 +01:00
|
|
|
public static void Mov(ILEmitterCtx context)
|
|
|
|
{
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 17:06:11 +01:00
|
|
|
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
|
2019-01-25 02:59:53 +01:00
|
|
|
|
|
|
|
EmitAluLoadOper2(context);
|
|
|
|
|
|
|
|
if (op.SetFlags)
|
|
|
|
{
|
|
|
|
context.EmitZnFlagCheck();
|
|
|
|
}
|
|
|
|
|
|
|
|
EmitAluStore(context);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void Sub(ILEmitterCtx context)
|
|
|
|
{
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 17:06:11 +01:00
|
|
|
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
|
2019-01-25 02:59:53 +01:00
|
|
|
|
|
|
|
EmitAluLoadOpers(context, setCarry: false);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Sub);
|
|
|
|
|
|
|
|
if (op.SetFlags)
|
|
|
|
{
|
|
|
|
context.EmitZnFlagCheck();
|
|
|
|
|
|
|
|
EmitSubsCCheck(context);
|
|
|
|
EmitSubsVCheck(context);
|
|
|
|
}
|
|
|
|
|
|
|
|
EmitAluStore(context);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitAluStore(ILEmitterCtx context)
|
|
|
|
{
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 17:06:11 +01:00
|
|
|
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
|
2019-01-25 02:59:53 +01:00
|
|
|
|
|
|
|
if (op.Rd == RegisterAlias.Aarch32Pc)
|
|
|
|
{
|
|
|
|
if (op.SetFlags)
|
|
|
|
{
|
|
|
|
//TODO: Load SPSR etc.
|
|
|
|
|
|
|
|
context.EmitLdflg((int)PState.TBit);
|
|
|
|
|
|
|
|
ILLabel lblThumb = new ILLabel();
|
|
|
|
ILLabel lblEnd = new ILLabel();
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Brtrue_S, lblThumb);
|
|
|
|
|
|
|
|
context.EmitLdc_I4(~3);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Br_S, lblEnd);
|
|
|
|
|
|
|
|
context.MarkLabel(lblThumb);
|
|
|
|
|
|
|
|
context.EmitLdc_I4(~1);
|
|
|
|
|
|
|
|
context.MarkLabel(lblEnd);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.And);
|
|
|
|
context.Emit(OpCodes.Conv_U8);
|
|
|
|
context.Emit(OpCodes.Ret);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
EmitAluWritePc(context);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
context.EmitStint(GetRegisterAlias(context.Mode, op.Rd));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitAluWritePc(ILEmitterCtx context)
|
|
|
|
{
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 17:06:11 +01:00
|
|
|
context.EmitStoreState();
|
|
|
|
|
2019-01-25 02:59:53 +01:00
|
|
|
if (IsThumb(context.CurrOp))
|
|
|
|
{
|
|
|
|
context.EmitLdc_I4(~1);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.And);
|
|
|
|
context.Emit(OpCodes.Conv_U8);
|
|
|
|
context.Emit(OpCodes.Ret);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
EmitBxWritePc(context);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|