2018-02-20 21:09:23 +01:00
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namespace Ryujinx.Graphics.Gpu
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2018-02-05 00:08:20 +01:00
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{
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2018-04-26 04:11:26 +02:00
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public class NsGpuMemoryMgr
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2018-02-05 00:08:20 +01:00
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{
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private const long AddrSize = 1L << 40;
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private const int PTLvl0Bits = 14;
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private const int PTLvl1Bits = 14;
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private const int PTPageBits = 12;
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private const int PTLvl0Size = 1 << PTLvl0Bits;
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private const int PTLvl1Size = 1 << PTLvl1Bits;
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private const int PageSize = 1 << PTPageBits;
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private const int PTLvl0Mask = PTLvl0Size - 1;
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private const int PTLvl1Mask = PTLvl1Size - 1;
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2018-02-10 01:13:18 +01:00
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private const int PageMask = PageSize - 1;
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2018-02-05 00:08:20 +01:00
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2018-02-28 00:45:07 +01:00
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private const int PTLvl0Bit = PTPageBits + PTLvl1Bits;
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2018-02-05 00:08:20 +01:00
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private const int PTLvl1Bit = PTPageBits;
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private const long PteUnmapped = -1;
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private const long PteReserved = -2;
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private long[][] PageTable;
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public NsGpuMemoryMgr()
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{
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PageTable = new long[PTLvl0Size][];
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}
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public long Map(long CpuAddr, long GpuAddr, long Size)
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{
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CpuAddr &= ~PageMask;
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GpuAddr &= ~PageMask;
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for (long Offset = 0; Offset < Size; Offset += PageSize)
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{
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if (GetPTAddr(GpuAddr + Offset) != PteReserved)
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{
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return Map(CpuAddr, Size);
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}
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}
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for (long Offset = 0; Offset < Size; Offset += PageSize)
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{
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SetPTAddr(GpuAddr + Offset, CpuAddr + Offset);
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}
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return GpuAddr;
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}
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2018-04-26 04:11:26 +02:00
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public void Unmap(long Position, long Size)
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{
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for (long Offset = 0; Offset < Size; Offset += PageSize)
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{
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SetPTAddr(Position + Offset, PteUnmapped);
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}
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}
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2018-02-05 00:08:20 +01:00
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public long Map(long CpuAddr, long Size)
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{
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CpuAddr &= ~PageMask;
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long Position = GetFreePosition(Size);
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2018-04-26 04:11:26 +02:00
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2018-02-05 00:08:20 +01:00
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if (Position != -1)
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{
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for (long Offset = 0; Offset < Size; Offset += PageSize)
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{
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SetPTAddr(Position + Offset, CpuAddr + Offset);
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}
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}
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return Position;
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}
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public long Reserve(long GpuAddr, long Size, long Align)
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{
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for (long Offset = 0; Offset < Size; Offset += PageSize)
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{
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if (HasPTAddr(GpuAddr + Offset))
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{
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return Reserve(Size, Align);
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}
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}
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for (long Offset = 0; Offset < Size; Offset += PageSize)
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{
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SetPTAddr(GpuAddr + Offset, PteReserved);
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}
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return GpuAddr;
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}
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public long Reserve(long Size, long Align)
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{
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long Position = GetFreePosition(Size, Align);
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if (Position != -1)
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{
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for (long Offset = 0; Offset < Size; Offset += PageSize)
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{
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SetPTAddr(Position + Offset, PteReserved);
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}
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}
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return Position;
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}
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private long GetFreePosition(long Size, long Align = 1)
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{
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long Position = 0;
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long FreeSize = 0;
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2018-02-10 01:13:18 +01:00
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if (Align < 1)
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{
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Align = 1;
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}
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2018-02-05 00:08:20 +01:00
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Align = (Align + PageMask) & ~PageMask;
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while (Position + FreeSize < AddrSize)
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{
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if (!HasPTAddr(Position + FreeSize))
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{
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FreeSize += PageSize;
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if (FreeSize >= Size)
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{
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return Position;
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}
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}
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else
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{
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Position += FreeSize + PageSize;
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FreeSize = 0;
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long Remainder = Position % Align;
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if (Remainder != 0)
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{
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Position = (Position - Remainder) + Align;
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}
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}
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}
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return -1;
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}
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public long GetCpuAddr(long Position)
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{
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long BasePos = GetPTAddr(Position);
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if (BasePos < 0)
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{
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return -1;
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}
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return BasePos + (Position & PageMask);
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}
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private bool HasPTAddr(long Position)
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{
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if (Position >> PTLvl0Bits + PTLvl1Bits + PTPageBits != 0)
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{
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return false;
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}
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long L0 = (Position >> PTLvl0Bit) & PTLvl0Mask;
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long L1 = (Position >> PTLvl1Bit) & PTLvl1Mask;
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if (PageTable[L0] == null)
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{
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return false;
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}
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return PageTable[L0][L1] != PteUnmapped;
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}
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private long GetPTAddr(long Position)
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{
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long L0 = (Position >> PTLvl0Bit) & PTLvl0Mask;
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long L1 = (Position >> PTLvl1Bit) & PTLvl1Mask;
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if (PageTable[L0] == null)
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{
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return -1;
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}
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return PageTable[L0][L1];
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}
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private void SetPTAddr(long Position, long TgtAddr)
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{
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long L0 = (Position >> PTLvl0Bit) & PTLvl0Mask;
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long L1 = (Position >> PTLvl1Bit) & PTLvl1Mask;
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if (PageTable[L0] == null)
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{
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PageTable[L0] = new long[PTLvl1Size];
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for (int Index = 0; Index < PTLvl1Size; Index++)
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{
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PageTable[L0][Index] = PteUnmapped;
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}
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}
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PageTable[L0][L1] = TgtAddr;
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}
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}
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}
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