Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
|
|
|
using ARMeilleure.Memory;
|
2018-12-18 06:33:36 +01:00
|
|
|
using Ryujinx.HLE.HOS.Kernel.Common;
|
|
|
|
using Ryujinx.HLE.HOS.Kernel.Ipc;
|
|
|
|
using Ryujinx.HLE.HOS.Kernel.Process;
|
2019-03-15 04:37:54 +01:00
|
|
|
using Ryujinx.HLE.HOS.Kernel.Threading;
|
2018-02-05 00:08:20 +01:00
|
|
|
using System;
|
|
|
|
using System.IO;
|
|
|
|
|
2018-08-17 01:47:36 +02:00
|
|
|
namespace Ryujinx.HLE.HOS.Ipc
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
|
|
|
static class IpcHandler
|
|
|
|
{
|
2018-12-18 06:33:36 +01:00
|
|
|
public static KernelResult IpcCall(
|
2019-01-18 23:26:39 +01:00
|
|
|
Switch device,
|
|
|
|
KProcess process,
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
|
|
|
IMemoryManager memory,
|
2019-03-15 04:37:54 +01:00
|
|
|
KThread thread,
|
2019-01-18 23:26:39 +01:00
|
|
|
KClientSession session,
|
|
|
|
IpcMessage request,
|
|
|
|
long cmdPtr)
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
IpcMessage response = new IpcMessage();
|
2018-02-05 00:08:20 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
using (MemoryStream raw = new MemoryStream(request.RawData))
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
BinaryReader reqReader = new BinaryReader(raw);
|
2018-02-05 00:08:20 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
if (request.Type == IpcMessageType.Request ||
|
|
|
|
request.Type == IpcMessageType.RequestWithContext)
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
response.Type = IpcMessageType.Response;
|
2018-02-05 00:08:20 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
using (MemoryStream resMs = new MemoryStream())
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
BinaryWriter resWriter = new BinaryWriter(resMs);
|
2018-02-05 00:08:20 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
ServiceCtx context = new ServiceCtx(
|
|
|
|
device,
|
|
|
|
process,
|
|
|
|
memory,
|
2019-03-15 04:37:54 +01:00
|
|
|
thread,
|
2018-12-06 12:16:24 +01:00
|
|
|
session,
|
|
|
|
request,
|
|
|
|
response,
|
|
|
|
reqReader,
|
|
|
|
resWriter);
|
2018-02-05 00:08:20 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
session.Service.CallMethod(context);
|
2018-02-05 00:08:20 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
response.RawData = resMs.ToArray();
|
2018-02-05 00:08:20 +01:00
|
|
|
}
|
|
|
|
}
|
2018-12-06 12:16:24 +01:00
|
|
|
else if (request.Type == IpcMessageType.Control ||
|
|
|
|
request.Type == IpcMessageType.ControlWithContext)
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
long magic = reqReader.ReadInt64();
|
|
|
|
long cmdId = reqReader.ReadInt64();
|
2018-02-05 00:08:20 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
switch (cmdId)
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2018-03-12 05:04:52 +01:00
|
|
|
case 0:
|
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
request = FillResponse(response, 0, session.Service.ConvertToDomain());
|
2018-03-12 05:04:52 +01:00
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case 3:
|
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
request = FillResponse(response, 0, 0x500);
|
2018-04-05 02:01:36 +02:00
|
|
|
|
2018-03-12 05:04:52 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2019-07-02 04:39:22 +02:00
|
|
|
// TODO: Whats the difference between IpcDuplicateSession/Ex?
|
2018-04-05 02:01:36 +02:00
|
|
|
case 2:
|
2018-03-12 05:04:52 +01:00
|
|
|
case 4:
|
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
int unknown = reqReader.ReadInt32();
|
2018-03-12 05:04:52 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
if (process.HandleTable.GenerateHandle(session, out int handle) != KernelResult.Success)
|
2018-09-23 20:11:46 +02:00
|
|
|
{
|
|
|
|
throw new InvalidOperationException("Out of handles!");
|
|
|
|
}
|
2018-03-12 05:04:52 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
response.HandleDesc = IpcHandleDesc.MakeMove(handle);
|
2018-03-12 05:04:52 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
request = FillResponse(response, 0);
|
2018-03-12 05:04:52 +01:00
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
2018-02-05 00:08:20 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
default: throw new NotImplementedException(cmdId.ToString());
|
2018-02-05 00:08:20 +01:00
|
|
|
}
|
|
|
|
}
|
2018-12-06 12:16:24 +01:00
|
|
|
else if (request.Type == IpcMessageType.CloseSession)
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2019-07-02 04:39:22 +02:00
|
|
|
// TODO
|
2019-10-11 17:53:45 +02:00
|
|
|
return KernelResult.PortRemoteClosed;
|
2018-02-05 00:08:20 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
throw new NotImplementedException(request.Type.ToString());
|
2018-02-05 00:08:20 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
memory.WriteBytes(cmdPtr, response.GetBytes(cmdPtr));
|
2018-02-05 00:08:20 +01:00
|
|
|
}
|
NvServices refactoring (#120)
* Initial implementation of NvMap/NvHostCtrl
* More work on NvHostCtrl
* Refactoring of nvservices, move GPU Vmm, make Vmm per-process, refactor most gpu devices, move Gpu to Core, fix CbBind
* Implement GetGpuTime, support CancelSynchronization, fix issue on InsertWaitingMutex, proper double buffering support (again, not working properly for commercial games, only hb)
* Try to fix perf regression reading/writing textures, moved syncpts and events to a UserCtx class, delete global state when the process exits, other minor tweaks
* Remove now unused code, add comment about probably wrong result codes
2018-05-07 20:53:23 +02:00
|
|
|
|
2018-12-18 06:33:36 +01:00
|
|
|
return KernelResult.Success;
|
2018-02-05 00:08:20 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
private static IpcMessage FillResponse(IpcMessage response, long result, params int[] values)
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
using (MemoryStream ms = new MemoryStream())
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
BinaryWriter writer = new BinaryWriter(ms);
|
2018-02-05 00:08:20 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
foreach (int value in values)
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
writer.Write(value);
|
2018-02-05 00:08:20 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
return FillResponse(response, result, ms.ToArray());
|
2018-02-05 00:08:20 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
private static IpcMessage FillResponse(IpcMessage response, long result, byte[] data = null)
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
response.Type = IpcMessageType.Response;
|
2018-02-05 00:08:20 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
using (MemoryStream ms = new MemoryStream())
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
BinaryWriter writer = new BinaryWriter(ms);
|
2018-02-05 00:08:20 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
writer.Write(IpcMagic.Sfco);
|
|
|
|
writer.Write(result);
|
2018-02-05 00:08:20 +01:00
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
if (data != null)
|
2018-02-05 00:08:20 +01:00
|
|
|
{
|
2018-12-06 12:16:24 +01:00
|
|
|
writer.Write(data);
|
2018-02-05 00:08:20 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
response.RawData = ms.ToArray();
|
2018-02-05 00:08:20 +01:00
|
|
|
}
|
|
|
|
|
2018-12-06 12:16:24 +01:00
|
|
|
return response;
|
2018-02-05 00:08:20 +01:00
|
|
|
}
|
|
|
|
}
|
2018-02-25 00:08:29 +01:00
|
|
|
}
|