mirror of
https://github.com/Ryujinx/Ryujinx.git
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160 lines
4.5 KiB
C#
160 lines
4.5 KiB
C#
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using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitMemoryHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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public static void Ld__Vms(ArmEmitterContext context)
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{
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EmitSimdMemMs(context, isLoad: true);
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}
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public static void Ld__Vss(ArmEmitterContext context)
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{
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EmitSimdMemSs(context, isLoad: true);
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}
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public static void St__Vms(ArmEmitterContext context)
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{
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EmitSimdMemMs(context, isLoad: false);
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}
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public static void St__Vss(ArmEmitterContext context)
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{
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EmitSimdMemSs(context, isLoad: false);
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}
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private static void EmitSimdMemMs(ArmEmitterContext context, bool isLoad)
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{
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OpCodeSimdMemMs op = (OpCodeSimdMemMs)context.CurrOp;
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Operand n = GetIntOrSP(context, op.Rn);
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long offset = 0;
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for (int rep = 0; rep < op.Reps; rep++)
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for (int elem = 0; elem < op.Elems; elem++)
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for (int sElem = 0; sElem < op.SElems; sElem++)
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{
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int rtt = (op.Rt + rep + sElem) & 0x1f;
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Operand tt = GetVec(rtt);
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Operand address = context.Add(n, Const(offset));
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if (isLoad)
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{
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EmitLoadSimd(context, address, tt, rtt, elem, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64 && elem == op.Elems - 1)
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{
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context.Copy(tt, context.VectorZeroUpper64(tt));
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}
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}
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else
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{
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EmitStoreSimd(context, address, rtt, elem, op.Size);
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}
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offset += 1 << op.Size;
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}
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if (op.WBack)
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{
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EmitSimdMemWBack(context, offset);
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}
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}
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private static void EmitSimdMemSs(ArmEmitterContext context, bool isLoad)
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{
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OpCodeSimdMemSs op = (OpCodeSimdMemSs)context.CurrOp;
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Operand n = GetIntOrSP(context, op.Rn);
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long offset = 0;
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if (op.Replicate)
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{
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// Only loads uses the replicate mode.
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Debug.Assert(isLoad, "Replicate mode is not valid for stores.");
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int elems = op.GetBytesCount() >> op.Size;
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for (int sElem = 0; sElem < op.SElems; sElem++)
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{
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int rt = (op.Rt + sElem) & 0x1f;
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Operand t = GetVec(rt);
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Operand address = context.Add(n, Const(offset));
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for (int index = 0; index < elems; index++)
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{
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EmitLoadSimd(context, address, t, rt, index, op.Size);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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context.Copy(t, context.VectorZeroUpper64(t));
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}
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offset += 1 << op.Size;
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}
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}
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else
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{
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for (int sElem = 0; sElem < op.SElems; sElem++)
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{
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int rt = (op.Rt + sElem) & 0x1f;
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Operand t = GetVec(rt);
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Operand address = context.Add(n, Const(offset));
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if (isLoad)
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{
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EmitLoadSimd(context, address, t, rt, op.Index, op.Size);
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}
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else
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{
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EmitStoreSimd(context, address, rt, op.Index, op.Size);
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}
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offset += 1 << op.Size;
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}
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}
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if (op.WBack)
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{
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EmitSimdMemWBack(context, offset);
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}
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}
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private static void EmitSimdMemWBack(ArmEmitterContext context, long offset)
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{
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OpCodeMemReg op = (OpCodeMemReg)context.CurrOp;
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Operand n = GetIntOrSP(context, op.Rn);
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Operand m;
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if (op.Rm != RegisterAlias.Zr)
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{
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m = GetIntOrZR(context, op.Rm);
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}
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else
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{
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m = Const(offset);
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}
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context.Copy(n, context.Add(n, m));
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}
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}
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}
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