Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
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using System;
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namespace ARMeilleure.CodeGen.X86
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{
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static class CallingConvention
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{
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private const int RegistersMask = 0xffff;
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public static int GetIntAvailableRegisters()
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{
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return RegistersMask & ~(1 << (int)X86Register.Rsp);
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}
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public static int GetVecAvailableRegisters()
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{
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return RegistersMask;
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}
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public static int GetIntCallerSavedRegisters()
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{
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if (GetCurrentCallConv() == CallConvName.Windows)
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{
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return (1 << (int)X86Register.Rax) |
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(1 << (int)X86Register.Rcx) |
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(1 << (int)X86Register.Rdx) |
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(1 << (int)X86Register.R8) |
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(1 << (int)X86Register.R9) |
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(1 << (int)X86Register.R10) |
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(1 << (int)X86Register.R11);
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}
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else /* if (GetCurrentCallConv() == CallConvName.SystemV) */
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{
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return (1 << (int)X86Register.Rax) |
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(1 << (int)X86Register.Rcx) |
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(1 << (int)X86Register.Rdx) |
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(1 << (int)X86Register.Rsi) |
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(1 << (int)X86Register.Rdi) |
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(1 << (int)X86Register.R8) |
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(1 << (int)X86Register.R9) |
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(1 << (int)X86Register.R10) |
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(1 << (int)X86Register.R11);
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}
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}
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public static int GetVecCallerSavedRegisters()
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{
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if (GetCurrentCallConv() == CallConvName.Windows)
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{
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return (1 << (int)X86Register.Xmm0) |
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(1 << (int)X86Register.Xmm1) |
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(1 << (int)X86Register.Xmm2) |
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(1 << (int)X86Register.Xmm3) |
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(1 << (int)X86Register.Xmm4) |
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(1 << (int)X86Register.Xmm5);
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}
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else /* if (GetCurrentCallConv() == CallConvName.SystemV) */
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{
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return RegistersMask;
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}
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}
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public static int GetIntCalleeSavedRegisters()
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{
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return GetIntCallerSavedRegisters() ^ RegistersMask;
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}
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public static int GetVecCalleeSavedRegisters()
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{
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return GetVecCallerSavedRegisters() ^ RegistersMask;
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}
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public static int GetArgumentsOnRegsCount()
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{
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return 4;
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}
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public static int GetIntArgumentsOnRegsCount()
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{
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return 6;
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}
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public static int GetVecArgumentsOnRegsCount()
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{
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return 8;
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}
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public static X86Register GetIntArgumentRegister(int index)
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{
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if (GetCurrentCallConv() == CallConvName.Windows)
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{
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switch (index)
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{
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case 0: return X86Register.Rcx;
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case 1: return X86Register.Rdx;
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case 2: return X86Register.R8;
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case 3: return X86Register.R9;
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}
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}
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else /* if (GetCurrentCallConv() == CallConvName.SystemV) */
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{
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switch (index)
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{
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case 0: return X86Register.Rdi;
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case 1: return X86Register.Rsi;
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case 2: return X86Register.Rdx;
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case 3: return X86Register.Rcx;
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case 4: return X86Register.R8;
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case 5: return X86Register.R9;
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}
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}
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throw new ArgumentOutOfRangeException(nameof(index));
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}
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public static X86Register GetVecArgumentRegister(int index)
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{
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int count;
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if (GetCurrentCallConv() == CallConvName.Windows)
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{
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count = 4;
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}
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else /* if (GetCurrentCallConv() == CallConvName.SystemV) */
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{
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count = 8;
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}
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if ((uint)index < count)
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{
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return X86Register.Xmm0 + index;
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}
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throw new ArgumentOutOfRangeException(nameof(index));
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}
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public static X86Register GetIntReturnRegister()
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{
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return X86Register.Rax;
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}
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public static X86Register GetIntReturnRegisterHigh()
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{
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return X86Register.Rdx;
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}
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public static X86Register GetVecReturnRegister()
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{
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return X86Register.Xmm0;
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}
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public static CallConvName GetCurrentCallConv()
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{
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2021-12-05 00:02:30 +01:00
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return OperatingSystem.IsWindows()
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
|
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? CallConvName.Windows
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: CallConvName.SystemV;
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}
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}
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}
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