2018-10-31 02:43:02 +01:00
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using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics.X86;
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using static ChocolArm64.Instructions.InstEmitAluHelper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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public static void Adc(ILEmitterCtx context) => EmitAdc(context, false);
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public static void Adcs(ILEmitterCtx context) => EmitAdc(context, true);
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private static void EmitAdc(ILEmitterCtx context, bool setFlags)
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{
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2019-01-25 02:59:53 +01:00
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EmitAluLoadOpers(context);
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2018-10-31 02:43:02 +01:00
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context.Emit(OpCodes.Add);
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context.EmitLdflg((int)PState.CBit);
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Type[] mthdTypes = new Type[] { typeof(bool) };
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MethodInfo mthdInfo = typeof(Convert).GetMethod(nameof(Convert.ToInt32), mthdTypes);
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context.EmitCall(mthdInfo);
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if (context.CurrOp.RegisterSize != RegisterSize.Int32)
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{
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context.Emit(OpCodes.Conv_U8);
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}
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context.Emit(OpCodes.Add);
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if (setFlags)
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{
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context.EmitZnFlagCheck();
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EmitAdcsCCheck(context);
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EmitAddsVCheck(context);
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}
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2019-01-25 02:59:53 +01:00
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EmitAluStore(context);
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2018-10-31 02:43:02 +01:00
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}
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2019-01-25 02:59:53 +01:00
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public static void Add(ILEmitterCtx context) => EmitAluOp(context, OpCodes.Add);
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2018-10-31 02:43:02 +01:00
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public static void Adds(ILEmitterCtx context)
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{
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2019-01-25 02:59:53 +01:00
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EmitAluLoadOpers(context);
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2018-10-31 02:43:02 +01:00
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context.Emit(OpCodes.Add);
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context.EmitZnFlagCheck();
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EmitAddsCCheck(context);
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EmitAddsVCheck(context);
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2019-01-25 02:59:53 +01:00
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EmitAluStoreS(context);
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2018-10-31 02:43:02 +01:00
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}
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2019-01-25 02:59:53 +01:00
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public static void And(ILEmitterCtx context) => EmitAluOp(context, OpCodes.And);
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2018-10-31 02:43:02 +01:00
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public static void Ands(ILEmitterCtx context)
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{
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2019-01-25 02:59:53 +01:00
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EmitAluLoadOpers(context);
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2018-10-31 02:43:02 +01:00
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context.Emit(OpCodes.And);
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EmitZeroCvFlags(context);
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context.EmitZnFlagCheck();
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2019-01-25 02:59:53 +01:00
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EmitAluStoreS(context);
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2018-10-31 02:43:02 +01:00
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}
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2019-01-25 02:59:53 +01:00
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public static void Asrv(ILEmitterCtx context) => EmitAluOpShift(context, OpCodes.Shr);
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2018-10-31 02:43:02 +01:00
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public static void Bic(ILEmitterCtx context) => EmitBic(context, false);
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public static void Bics(ILEmitterCtx context) => EmitBic(context, true);
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private static void EmitBic(ILEmitterCtx context, bool setFlags)
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{
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2019-01-25 02:59:53 +01:00
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EmitAluLoadOpers(context);
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2018-10-31 02:43:02 +01:00
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context.Emit(OpCodes.Not);
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context.Emit(OpCodes.And);
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if (setFlags)
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{
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EmitZeroCvFlags(context);
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context.EmitZnFlagCheck();
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}
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2019-01-25 02:59:53 +01:00
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EmitAluStore(context, setFlags);
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2018-10-31 02:43:02 +01:00
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}
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public static void Cls(ILEmitterCtx context)
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{
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OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp;
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context.EmitLdintzr(op.Rn);
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context.EmitLdc_I4(op.RegisterSize == RegisterSize.Int32 ? 32 : 64);
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SoftFallback.EmitCall(context, nameof(SoftFallback.CountLeadingSigns));
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context.EmitStintzr(op.Rd);
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}
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public static void Clz(ILEmitterCtx context)
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{
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OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp;
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context.EmitLdintzr(op.Rn);
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if (Lzcnt.IsSupported)
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{
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Type tValue = op.RegisterSize == RegisterSize.Int32 ? typeof(uint) : typeof(ulong);
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context.EmitCall(typeof(Lzcnt).GetMethod(nameof(Lzcnt.LeadingZeroCount), new Type[] { tValue }));
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}
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else
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{
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context.EmitLdc_I4(op.RegisterSize == RegisterSize.Int32 ? 32 : 64);
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SoftFallback.EmitCall(context, nameof(SoftFallback.CountLeadingZeros));
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}
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context.EmitStintzr(op.Rd);
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}
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public static void Eon(ILEmitterCtx context)
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{
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2019-01-25 02:59:53 +01:00
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EmitAluLoadOpers(context);
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2018-10-31 02:43:02 +01:00
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context.Emit(OpCodes.Not);
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context.Emit(OpCodes.Xor);
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2019-01-25 02:59:53 +01:00
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EmitAluStore(context);
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2018-10-31 02:43:02 +01:00
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}
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2019-01-25 02:59:53 +01:00
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public static void Eor(ILEmitterCtx context) => EmitAluOp(context, OpCodes.Xor);
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2018-10-31 02:43:02 +01:00
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public static void Extr(ILEmitterCtx context)
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{
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//TODO: Ensure that the Shift is valid for the Is64Bits.
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OpCodeAluRs64 op = (OpCodeAluRs64)context.CurrOp;
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context.EmitLdintzr(op.Rm);
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if (op.Shift > 0)
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{
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context.EmitLdc_I4(op.Shift);
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context.Emit(OpCodes.Shr_Un);
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context.EmitLdintzr(op.Rn);
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context.EmitLdc_I4(op.GetBitsCount() - op.Shift);
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context.Emit(OpCodes.Shl);
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context.Emit(OpCodes.Or);
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}
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2019-01-25 02:59:53 +01:00
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EmitAluStore(context);
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2018-10-31 02:43:02 +01:00
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}
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2019-01-25 02:59:53 +01:00
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public static void Lslv(ILEmitterCtx context) => EmitAluOpShift(context, OpCodes.Shl);
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public static void Lsrv(ILEmitterCtx context) => EmitAluOpShift(context, OpCodes.Shr_Un);
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2018-10-31 02:43:02 +01:00
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public static void Sbc(ILEmitterCtx context) => EmitSbc(context, false);
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public static void Sbcs(ILEmitterCtx context) => EmitSbc(context, true);
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private static void EmitSbc(ILEmitterCtx context, bool setFlags)
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{
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2019-01-25 02:59:53 +01:00
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EmitAluLoadOpers(context);
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2018-10-31 02:43:02 +01:00
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context.Emit(OpCodes.Sub);
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context.EmitLdflg((int)PState.CBit);
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Type[] mthdTypes = new Type[] { typeof(bool) };
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MethodInfo mthdInfo = typeof(Convert).GetMethod(nameof(Convert.ToInt32), mthdTypes);
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context.EmitCall(mthdInfo);
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context.EmitLdc_I4(1);
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context.Emit(OpCodes.Xor);
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if (context.CurrOp.RegisterSize != RegisterSize.Int32)
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{
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context.Emit(OpCodes.Conv_U8);
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}
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context.Emit(OpCodes.Sub);
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if (setFlags)
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{
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context.EmitZnFlagCheck();
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EmitSbcsCCheck(context);
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EmitSubsVCheck(context);
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}
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2019-01-25 02:59:53 +01:00
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EmitAluStore(context);
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2018-10-31 02:43:02 +01:00
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}
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2019-01-25 02:59:53 +01:00
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public static void Sub(ILEmitterCtx context) => EmitAluOp(context, OpCodes.Sub);
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2018-10-31 02:43:02 +01:00
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public static void Subs(ILEmitterCtx context)
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{
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context.TryOptMarkCondWithoutCmp();
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2019-01-25 02:59:53 +01:00
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EmitAluLoadOpers(context);
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2018-10-31 02:43:02 +01:00
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context.Emit(OpCodes.Sub);
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context.EmitZnFlagCheck();
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EmitSubsCCheck(context);
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EmitSubsVCheck(context);
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2019-01-25 02:59:53 +01:00
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EmitAluStoreS(context);
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2018-10-31 02:43:02 +01:00
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}
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public static void Orn(ILEmitterCtx context)
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{
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2019-01-25 02:59:53 +01:00
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EmitAluLoadOpers(context);
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2018-10-31 02:43:02 +01:00
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context.Emit(OpCodes.Not);
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context.Emit(OpCodes.Or);
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2019-01-25 02:59:53 +01:00
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EmitAluStore(context);
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2018-10-31 02:43:02 +01:00
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}
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2019-01-25 02:59:53 +01:00
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public static void Orr(ILEmitterCtx context) => EmitAluOp(context, OpCodes.Or);
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2018-10-31 02:43:02 +01:00
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public static void Rbit(ILEmitterCtx context) => EmitFallback32_64(context,
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nameof(SoftFallback.ReverseBits32),
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nameof(SoftFallback.ReverseBits64));
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public static void Rev16(ILEmitterCtx context) => EmitFallback32_64(context,
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nameof(SoftFallback.ReverseBytes16_32),
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nameof(SoftFallback.ReverseBytes16_64));
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public static void Rev32(ILEmitterCtx context) => EmitFallback32_64(context,
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nameof(SoftFallback.ReverseBytes32_32),
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nameof(SoftFallback.ReverseBytes32_64));
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private static void EmitFallback32_64(ILEmitterCtx context, string name32, string name64)
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{
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OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp;
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context.EmitLdintzr(op.Rn);
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if (op.RegisterSize == RegisterSize.Int32)
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{
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SoftFallback.EmitCall(context, name32);
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}
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else
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{
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SoftFallback.EmitCall(context, name64);
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}
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context.EmitStintzr(op.Rd);
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}
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public static void Rev64(ILEmitterCtx context)
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{
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OpCodeAlu64 op = (OpCodeAlu64)context.CurrOp;
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context.EmitLdintzr(op.Rn);
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SoftFallback.EmitCall(context, nameof(SoftFallback.ReverseBytes64));
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context.EmitStintzr(op.Rd);
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}
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public static void Rorv(ILEmitterCtx context)
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{
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2019-01-25 02:59:53 +01:00
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EmitAluLoadRn(context);
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EmitAluLoadShift(context);
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2018-10-31 02:43:02 +01:00
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context.Emit(OpCodes.Shr_Un);
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2019-01-25 02:59:53 +01:00
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EmitAluLoadRn(context);
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2018-10-31 02:43:02 +01:00
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context.EmitLdc_I4(context.CurrOp.GetBitsCount());
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2019-01-25 02:59:53 +01:00
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EmitAluLoadShift(context);
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2018-10-31 02:43:02 +01:00
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context.Emit(OpCodes.Sub);
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context.Emit(OpCodes.Shl);
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context.Emit(OpCodes.Or);
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2019-01-25 02:59:53 +01:00
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EmitAluStore(context);
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2018-10-31 02:43:02 +01:00
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}
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public static void Sdiv(ILEmitterCtx context) => EmitDiv(context, OpCodes.Div);
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public static void Udiv(ILEmitterCtx context) => EmitDiv(context, OpCodes.Div_Un);
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private static void EmitDiv(ILEmitterCtx context, OpCode ilOp)
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{
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//If Rm == 0, Rd = 0 (division by zero).
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context.EmitLdc_I(0);
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2019-01-25 02:59:53 +01:00
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EmitAluLoadRm(context);
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2018-10-31 02:43:02 +01:00
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context.EmitLdc_I(0);
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ILLabel badDiv = new ILLabel();
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context.Emit(OpCodes.Beq_S, badDiv);
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context.Emit(OpCodes.Pop);
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if (ilOp == OpCodes.Div)
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{
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//If Rn == INT_MIN && Rm == -1, Rd = INT_MIN (overflow).
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long intMin = 1L << (context.CurrOp.GetBitsCount() - 1);
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context.EmitLdc_I(intMin);
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2019-01-25 02:59:53 +01:00
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EmitAluLoadRn(context);
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2018-10-31 02:43:02 +01:00
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context.EmitLdc_I(intMin);
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context.Emit(OpCodes.Ceq);
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2019-01-25 02:59:53 +01:00
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EmitAluLoadRm(context);
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2018-10-31 02:43:02 +01:00
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context.EmitLdc_I(-1);
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context.Emit(OpCodes.Ceq);
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context.Emit(OpCodes.And);
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context.Emit(OpCodes.Brtrue_S, badDiv);
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context.Emit(OpCodes.Pop);
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}
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2019-01-25 02:59:53 +01:00
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EmitAluLoadRn(context);
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EmitAluLoadRm(context);
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2018-10-31 02:43:02 +01:00
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|
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context.Emit(ilOp);
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context.MarkLabel(badDiv);
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2019-01-25 02:59:53 +01:00
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EmitAluStore(context);
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2018-10-31 02:43:02 +01:00
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}
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|
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2019-01-25 02:59:53 +01:00
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|
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private static void EmitAluOp(ILEmitterCtx context, OpCode ilOp)
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2018-10-31 02:43:02 +01:00
|
|
|
{
|
2019-01-25 02:59:53 +01:00
|
|
|
EmitAluLoadOpers(context);
|
2018-10-31 02:43:02 +01:00
|
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|
|
|
|
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context.Emit(ilOp);
|
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|
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|
2019-01-25 02:59:53 +01:00
|
|
|
EmitAluStore(context);
|
2018-10-31 02:43:02 +01:00
|
|
|
}
|
|
|
|
|
2019-01-25 02:59:53 +01:00
|
|
|
private static void EmitAluOpShift(ILEmitterCtx context, OpCode ilOp)
|
2018-10-31 02:43:02 +01:00
|
|
|
{
|
2019-01-25 02:59:53 +01:00
|
|
|
EmitAluLoadRn(context);
|
|
|
|
EmitAluLoadShift(context);
|
2018-10-31 02:43:02 +01:00
|
|
|
|
|
|
|
context.Emit(ilOp);
|
|
|
|
|
2019-01-25 02:59:53 +01:00
|
|
|
EmitAluStore(context);
|
2018-10-31 02:43:02 +01:00
|
|
|
}
|
|
|
|
|
2019-01-25 02:59:53 +01:00
|
|
|
private static void EmitAluLoadShift(ILEmitterCtx context)
|
2018-10-31 02:43:02 +01:00
|
|
|
{
|
2019-01-25 02:59:53 +01:00
|
|
|
EmitAluLoadRm(context);
|
2018-10-31 02:43:02 +01:00
|
|
|
|
|
|
|
context.EmitLdc_I(context.CurrOp.GetBitsCount() - 1);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.And);
|
|
|
|
|
|
|
|
//Note: Only 32-bits shift values are valid, so when the value is 64-bits
|
|
|
|
//we need to cast it to a 32-bits integer. This is fine because we
|
|
|
|
//AND the value and only keep the lower 5 or 6 bits anyway -- it
|
|
|
|
//could very well fit on a byte.
|
|
|
|
if (context.CurrOp.RegisterSize != RegisterSize.Int32)
|
|
|
|
{
|
|
|
|
context.Emit(OpCodes.Conv_I4);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitZeroCvFlags(ILEmitterCtx context)
|
|
|
|
{
|
|
|
|
context.EmitLdc_I4(0);
|
|
|
|
|
|
|
|
context.EmitStflg((int)PState.VBit);
|
|
|
|
|
|
|
|
context.EmitLdc_I4(0);
|
|
|
|
|
|
|
|
context.EmitStflg((int)PState.CBit);
|
|
|
|
}
|
2019-01-25 02:59:53 +01:00
|
|
|
|
|
|
|
public static void EmitAluStore(ILEmitterCtx context) => EmitAluStore(context, false);
|
|
|
|
public static void EmitAluStoreS(ILEmitterCtx context) => EmitAluStore(context, true);
|
|
|
|
|
|
|
|
public static void EmitAluStore(ILEmitterCtx context, bool setFlags)
|
|
|
|
{
|
|
|
|
IOpCodeAlu64 op = (IOpCodeAlu64)context.CurrOp;
|
|
|
|
|
|
|
|
if (setFlags || op is IOpCodeAluRs64)
|
|
|
|
{
|
|
|
|
context.EmitStintzr(op.Rd);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
context.EmitStint(op.Rd);
|
|
|
|
}
|
|
|
|
}
|
2018-10-31 02:43:02 +01:00
|
|
|
}
|
|
|
|
}
|