2018-02-17 22:06:11 +01:00
|
|
|
using ChocolArm64.Decoder;
|
|
|
|
using ChocolArm64.State;
|
|
|
|
using ChocolArm64.Translation;
|
|
|
|
using System;
|
|
|
|
using System.Reflection;
|
2018-07-14 18:13:02 +02:00
|
|
|
using System.Reflection.Emit;
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
using System.Runtime.CompilerServices;
|
2018-05-12 01:10:27 +02:00
|
|
|
using System.Runtime.Intrinsics;
|
|
|
|
using System.Runtime.Intrinsics.X86;
|
2018-02-17 22:06:11 +01:00
|
|
|
|
|
|
|
namespace ChocolArm64.Instruction
|
|
|
|
{
|
|
|
|
static class AInstEmitSimdHelper
|
|
|
|
{
|
|
|
|
[Flags]
|
|
|
|
public enum OperFlags
|
|
|
|
{
|
|
|
|
Rd = 1 << 0,
|
|
|
|
Rn = 1 << 1,
|
|
|
|
Rm = 1 << 2,
|
|
|
|
Ra = 1 << 3,
|
|
|
|
|
|
|
|
RnRm = Rn | Rm,
|
|
|
|
RdRn = Rd | Rn,
|
|
|
|
RaRnRm = Ra | Rn | Rm,
|
|
|
|
RdRnRm = Rd | Rn | Rm
|
|
|
|
}
|
|
|
|
|
|
|
|
public static int GetImmShl(AOpCodeSimdShImm Op)
|
|
|
|
{
|
|
|
|
return Op.Imm - (8 << Op.Size);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static int GetImmShr(AOpCodeSimdShImm Op)
|
|
|
|
{
|
|
|
|
return (8 << (Op.Size + 1)) - Op.Imm;
|
|
|
|
}
|
|
|
|
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
2018-05-12 01:10:27 +02:00
|
|
|
public static void EmitSse2Call(AILEmitterCtx Context, string Name)
|
|
|
|
{
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
EmitSseCall(Context, Name, typeof(Sse2));
|
|
|
|
}
|
2018-05-12 01:10:27 +02:00
|
|
|
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
|
|
|
public static void EmitSse41Call(AILEmitterCtx Context, string Name)
|
|
|
|
{
|
|
|
|
EmitSseCall(Context, Name, typeof(Sse41));
|
|
|
|
}
|
|
|
|
|
|
|
|
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
|
|
|
public static void EmitSse42Call(AILEmitterCtx Context, string Name)
|
|
|
|
{
|
|
|
|
EmitSseCall(Context, Name, typeof(Sse42));
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitSseCall(AILEmitterCtx Context, string Name, Type Type)
|
|
|
|
{
|
|
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
2018-05-12 01:10:27 +02:00
|
|
|
|
|
|
|
void Ldvec(int Reg)
|
|
|
|
{
|
|
|
|
Context.EmitLdvec(Reg);
|
|
|
|
|
|
|
|
switch (Op.Size)
|
|
|
|
{
|
|
|
|
case 0: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToSByte)); break;
|
|
|
|
case 1: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToInt16)); break;
|
|
|
|
case 2: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToInt32)); break;
|
|
|
|
case 3: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToInt64)); break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
Ldvec(Op.Rn);
|
|
|
|
|
|
|
|
Type BaseType = null;
|
|
|
|
|
|
|
|
switch (Op.Size)
|
|
|
|
{
|
|
|
|
case 0: BaseType = typeof(Vector128<sbyte>); break;
|
|
|
|
case 1: BaseType = typeof(Vector128<short>); break;
|
|
|
|
case 2: BaseType = typeof(Vector128<int>); break;
|
|
|
|
case 3: BaseType = typeof(Vector128<long>); break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Op is AOpCodeSimdReg BinOp)
|
|
|
|
{
|
|
|
|
Ldvec(BinOp.Rm);
|
|
|
|
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType, BaseType }));
|
2018-05-12 01:10:27 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType }));
|
2018-05-12 01:10:27 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
switch (Op.Size)
|
|
|
|
{
|
|
|
|
case 0: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSByteToSingle)); break;
|
|
|
|
case 1: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInt16ToSingle)); break;
|
|
|
|
case 2: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInt32ToSingle)); break;
|
|
|
|
case 3: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInt64ToSingle)); break;
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
|
|
{
|
|
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
public static void EmitSseOrSse2CallF(AILEmitterCtx Context, string Name)
|
2018-05-12 01:10:27 +02:00
|
|
|
{
|
|
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
|
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
|
|
|
|
void Ldvec(int Reg)
|
|
|
|
{
|
|
|
|
Context.EmitLdvec(Reg);
|
|
|
|
|
|
|
|
if (SizeF == 1)
|
|
|
|
{
|
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToDouble));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
Ldvec(Op.Rn);
|
|
|
|
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
Type Type;
|
|
|
|
Type BaseType;
|
2018-05-12 01:10:27 +02:00
|
|
|
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
if (SizeF == 0)
|
2018-05-12 01:10:27 +02:00
|
|
|
{
|
2018-07-03 08:31:48 +02:00
|
|
|
Type = typeof(Sse);
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
BaseType = typeof(Vector128<float>);
|
2018-05-12 01:10:27 +02:00
|
|
|
}
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
else /* if (SizeF == 1) */
|
2018-05-12 01:10:27 +02:00
|
|
|
{
|
2018-07-03 08:31:48 +02:00
|
|
|
Type = typeof(Sse2);
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
BaseType = typeof(Vector128<double>);
|
2018-05-12 01:10:27 +02:00
|
|
|
}
|
|
|
|
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
if (Op is AOpCodeSimdReg BinOp)
|
2018-05-12 01:10:27 +02:00
|
|
|
{
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
Ldvec(BinOp.Rm);
|
|
|
|
|
|
|
|
Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType, BaseType }));
|
2018-05-12 01:10:27 +02:00
|
|
|
}
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
else
|
2018-05-12 01:10:27 +02:00
|
|
|
{
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-26 03:32:29 +02:00
|
|
|
Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType }));
|
2018-05-12 01:10:27 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (SizeF == 1)
|
|
|
|
{
|
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorDoubleToSingle));
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
|
|
{
|
|
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
public static void EmitUnaryMathCall(AILEmitterCtx Context, string Name)
|
|
|
|
{
|
|
|
|
IAOpCodeSimd Op = (IAOpCodeSimd)Context.CurrOp;
|
|
|
|
|
2018-02-24 22:47:08 +01:00
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
MethodInfo MthdInfo;
|
|
|
|
|
2018-02-24 22:47:08 +01:00
|
|
|
if (SizeF == 0)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
MthdInfo = typeof(MathF).GetMethod(Name, new Type[] { typeof(float) });
|
|
|
|
}
|
2018-02-24 22:47:08 +01:00
|
|
|
else /* if (SizeF == 1) */
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
MthdInfo = typeof(Math).GetMethod(Name, new Type[] { typeof(double) });
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitCall(MthdInfo);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitBinaryMathCall(AILEmitterCtx Context, string Name)
|
|
|
|
{
|
|
|
|
IAOpCodeSimd Op = (IAOpCodeSimd)Context.CurrOp;
|
|
|
|
|
2018-02-24 22:47:08 +01:00
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
MethodInfo MthdInfo;
|
|
|
|
|
2018-02-24 22:47:08 +01:00
|
|
|
if (SizeF == 0)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
MthdInfo = typeof(MathF).GetMethod(Name, new Type[] { typeof(float), typeof(float) });
|
|
|
|
}
|
2018-02-24 22:47:08 +01:00
|
|
|
else /* if (SizeF == 1) */
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
MthdInfo = typeof(Math).GetMethod(Name, new Type[] { typeof(double), typeof(double) });
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitCall(MthdInfo);
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:59:37 +01:00
|
|
|
public static void EmitRoundMathCall(AILEmitterCtx Context, MidpointRounding RoundMode)
|
|
|
|
{
|
|
|
|
IAOpCodeSimd Op = (IAOpCodeSimd)Context.CurrOp;
|
|
|
|
|
2018-02-24 22:47:08 +01:00
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
|
2018-02-17 22:59:37 +01:00
|
|
|
Context.EmitLdc_I4((int)RoundMode);
|
|
|
|
|
|
|
|
MethodInfo MthdInfo;
|
|
|
|
|
|
|
|
Type[] Types = new Type[] { null, typeof(MidpointRounding) };
|
|
|
|
|
2018-02-24 22:47:08 +01:00
|
|
|
Types[0] = SizeF == 0
|
2018-02-17 22:59:37 +01:00
|
|
|
? typeof(float)
|
|
|
|
: typeof(double);
|
|
|
|
|
2018-02-24 22:47:08 +01:00
|
|
|
if (SizeF == 0)
|
2018-02-17 22:59:37 +01:00
|
|
|
{
|
|
|
|
MthdInfo = typeof(MathF).GetMethod(nameof(MathF.Round), Types);
|
|
|
|
}
|
2018-02-24 22:47:08 +01:00
|
|
|
else /* if (SizeF == 1) */
|
2018-02-17 22:59:37 +01:00
|
|
|
{
|
|
|
|
MthdInfo = typeof(Math).GetMethod(nameof(Math.Round), Types);
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitCall(MthdInfo);
|
|
|
|
}
|
|
|
|
|
2018-04-06 01:36:19 +02:00
|
|
|
public static void EmitUnarySoftFloatCall(AILEmitterCtx Context, string Name)
|
|
|
|
{
|
|
|
|
IAOpCodeSimd Op = (IAOpCodeSimd)Context.CurrOp;
|
|
|
|
|
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
|
|
|
|
MethodInfo MthdInfo;
|
|
|
|
|
|
|
|
if (SizeF == 0)
|
|
|
|
{
|
|
|
|
MthdInfo = typeof(ASoftFloat).GetMethod(Name, new Type[] { typeof(float) });
|
|
|
|
}
|
|
|
|
else /* if (SizeF == 1) */
|
|
|
|
{
|
|
|
|
MthdInfo = typeof(ASoftFloat).GetMethod(Name, new Type[] { typeof(double) });
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitCall(MthdInfo);
|
|
|
|
}
|
|
|
|
|
2018-07-08 21:54:47 +02:00
|
|
|
public static void EmitBinarySoftFloatCall(AILEmitterCtx Context, string Name)
|
|
|
|
{
|
|
|
|
IAOpCodeSimd Op = (IAOpCodeSimd)Context.CurrOp;
|
|
|
|
|
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
|
|
|
|
MethodInfo MthdInfo;
|
|
|
|
|
|
|
|
if (SizeF == 0)
|
|
|
|
{
|
|
|
|
MthdInfo = typeof(ASoftFloat).GetMethod(Name, new Type[] { typeof(float), typeof(float) });
|
|
|
|
}
|
|
|
|
else /* if (SizeF == 1) */
|
|
|
|
{
|
|
|
|
MthdInfo = typeof(ASoftFloat).GetMethod(Name, new Type[] { typeof(double), typeof(double) });
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitCall(MthdInfo);
|
|
|
|
}
|
|
|
|
|
2018-04-08 21:08:57 +02:00
|
|
|
public static void EmitScalarBinaryOpByElemF(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
AOpCodeSimdRegElemF Op = (AOpCodeSimdRegElemF)Context.CurrOp;
|
|
|
|
|
|
|
|
EmitScalarOpByElemF(Context, Emit, Op.Index, Ternary: false);
|
|
|
|
}
|
|
|
|
|
2018-06-29 01:51:38 +02:00
|
|
|
public static void EmitScalarTernaryOpByElemF(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
AOpCodeSimdRegElemF Op = (AOpCodeSimdRegElemF)Context.CurrOp;
|
|
|
|
|
|
|
|
EmitScalarOpByElemF(Context, Emit, Op.Index, Ternary: true);
|
|
|
|
}
|
|
|
|
|
2018-04-08 21:08:57 +02:00
|
|
|
public static void EmitScalarOpByElemF(AILEmitterCtx Context, Action Emit, int Elem, bool Ternary)
|
|
|
|
{
|
|
|
|
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
|
|
|
|
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
|
|
|
|
if (Ternary)
|
|
|
|
{
|
|
|
|
EmitVectorExtractF(Context, Op.Rd, 0, SizeF);
|
|
|
|
}
|
|
|
|
|
|
|
|
EmitVectorExtractF(Context, Op.Rn, 0, SizeF);
|
|
|
|
EmitVectorExtractF(Context, Op.Rm, Elem, SizeF);
|
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
|
|
|
EmitScalarSetF(Context, Op.Rd, SizeF);
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
public static void EmitScalarUnaryOpSx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitScalarOp(Context, Emit, OperFlags.Rn, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitScalarBinaryOpSx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitScalarOp(Context, Emit, OperFlags.RnRm, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitScalarUnaryOpZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitScalarOp(Context, Emit, OperFlags.Rn, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitScalarBinaryOpZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitScalarOp(Context, Emit, OperFlags.RnRm, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitScalarTernaryOpZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitScalarOp(Context, Emit, OperFlags.RdRnRm, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitScalarOp(AILEmitterCtx Context, Action Emit, OperFlags Opers, bool Signed)
|
|
|
|
{
|
2018-02-20 18:39:03 +01:00
|
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
2018-02-17 22:06:11 +01:00
|
|
|
|
|
|
|
if (Opers.HasFlag(OperFlags.Rd))
|
|
|
|
{
|
|
|
|
EmitVectorExtract(Context, Op.Rd, 0, Op.Size, Signed);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Opers.HasFlag(OperFlags.Rn))
|
|
|
|
{
|
|
|
|
EmitVectorExtract(Context, Op.Rn, 0, Op.Size, Signed);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Opers.HasFlag(OperFlags.Rm))
|
|
|
|
{
|
2018-02-20 18:39:03 +01:00
|
|
|
EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, 0, Op.Size, Signed);
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
|
|
|
EmitScalarSet(Context, Op.Rd, Op.Size);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitScalarUnaryOpF(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitScalarOpF(Context, Emit, OperFlags.Rn);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitScalarBinaryOpF(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitScalarOpF(Context, Emit, OperFlags.RnRm);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitScalarTernaryRaOpF(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitScalarOpF(Context, Emit, OperFlags.RaRnRm);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitScalarOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers)
|
|
|
|
{
|
|
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
|
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
|
|
|
|
if (Opers.HasFlag(OperFlags.Ra))
|
|
|
|
{
|
|
|
|
EmitVectorExtractF(Context, ((AOpCodeSimdReg)Op).Ra, 0, SizeF);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Opers.HasFlag(OperFlags.Rn))
|
|
|
|
{
|
|
|
|
EmitVectorExtractF(Context, Op.Rn, 0, SizeF);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Opers.HasFlag(OperFlags.Rm))
|
|
|
|
{
|
|
|
|
EmitVectorExtractF(Context, ((AOpCodeSimdReg)Op).Rm, 0, SizeF);
|
|
|
|
}
|
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
|
|
|
EmitScalarSetF(Context, Op.Rd, SizeF);
|
|
|
|
}
|
|
|
|
|
2018-03-10 03:41:05 +01:00
|
|
|
public static void EmitVectorUnaryOpF(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorOpF(Context, Emit, OperFlags.Rn);
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
public static void EmitVectorBinaryOpF(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorOpF(Context, Emit, OperFlags.RnRm);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorTernaryOpF(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorOpF(Context, Emit, OperFlags.RdRnRm);
|
|
|
|
}
|
|
|
|
|
2018-02-18 05:57:33 +01:00
|
|
|
public static void EmitVectorOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
2018-03-10 04:00:31 +01:00
|
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
2018-02-17 22:06:11 +01:00
|
|
|
|
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
int Bytes = Op.GetBitsCount() >> 3;
|
2018-07-19 02:06:28 +02:00
|
|
|
int Elems = Bytes >> SizeF + 2;
|
2018-02-17 22:06:11 +01:00
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
bool Rd = (Opers & OperFlags.Rd) != 0;
|
|
|
|
bool Rn = (Opers & OperFlags.Rn) != 0;
|
|
|
|
bool Rm = (Opers & OperFlags.Rm) != 0;
|
|
|
|
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
2018-07-19 02:06:28 +02:00
|
|
|
if (Rd)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
EmitVectorExtractF(Context, Op.Rd, Index, SizeF);
|
|
|
|
}
|
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
if (Rn)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
|
|
|
|
}
|
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
if (Rm)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
2018-03-10 04:00:31 +01:00
|
|
|
EmitVectorExtractF(Context, ((AOpCodeSimdReg)Op).Rm, Index, SizeF);
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
|
|
|
EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
|
|
{
|
|
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-03-05 20:18:37 +01:00
|
|
|
public static void EmitVectorBinaryOpByElemF(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
AOpCodeSimdRegElemF Op = (AOpCodeSimdRegElemF)Context.CurrOp;
|
|
|
|
|
|
|
|
EmitVectorOpByElemF(Context, Emit, Op.Index, Ternary: false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorTernaryOpByElemF(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
AOpCodeSimdRegElemF Op = (AOpCodeSimdRegElemF)Context.CurrOp;
|
|
|
|
|
|
|
|
EmitVectorOpByElemF(Context, Emit, Op.Index, Ternary: true);
|
|
|
|
}
|
|
|
|
|
2018-02-18 06:13:42 +01:00
|
|
|
public static void EmitVectorOpByElemF(AILEmitterCtx Context, Action Emit, int Elem, bool Ternary)
|
2018-02-18 05:57:33 +01:00
|
|
|
{
|
|
|
|
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
|
|
|
|
|
|
|
int SizeF = Op.Size & 1;
|
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
int Bytes = Op.GetBitsCount() >> 3;
|
2018-07-19 02:06:28 +02:00
|
|
|
int Elems = Bytes >> SizeF + 2;
|
2018-02-18 05:57:33 +01:00
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
2018-02-18 05:57:33 +01:00
|
|
|
{
|
2018-02-18 06:13:42 +01:00
|
|
|
if (Ternary)
|
|
|
|
{
|
|
|
|
EmitVectorExtractF(Context, Op.Rd, Index, SizeF);
|
|
|
|
}
|
|
|
|
|
2018-02-18 05:57:33 +01:00
|
|
|
EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
|
|
|
|
EmitVectorExtractF(Context, Op.Rm, Elem, SizeF);
|
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
|
|
|
EmitVectorInsertTmpF(Context, Index, SizeF);
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitLdvectmp();
|
|
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
|
|
{
|
|
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
public static void EmitVectorUnaryOpSx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorOp(Context, Emit, OperFlags.Rn, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorBinaryOpSx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorOp(Context, Emit, OperFlags.RnRm, true);
|
|
|
|
}
|
|
|
|
|
2018-06-30 17:40:41 +02:00
|
|
|
public static void EmitVectorTernaryOpSx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorOp(Context, Emit, OperFlags.RdRnRm, true);
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
public static void EmitVectorUnaryOpZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorOp(Context, Emit, OperFlags.Rn, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorBinaryOpZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorOp(Context, Emit, OperFlags.RnRm, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorTernaryOpZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorOp(Context, Emit, OperFlags.RdRnRm, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorOp(AILEmitterCtx Context, Action Emit, OperFlags Opers, bool Signed)
|
|
|
|
{
|
|
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
int Bytes = Op.GetBitsCount() >> 3;
|
|
|
|
int Elems = Bytes >> Op.Size;
|
2018-02-17 22:06:11 +01:00
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
bool Rd = (Opers & OperFlags.Rd) != 0;
|
|
|
|
bool Rn = (Opers & OperFlags.Rn) != 0;
|
|
|
|
bool Rm = (Opers & OperFlags.Rm) != 0;
|
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
2018-07-19 02:06:28 +02:00
|
|
|
if (Rd)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
|
|
|
|
}
|
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
if (Rn)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
|
|
|
|
}
|
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
if (Rm)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Op.Size, Signed);
|
|
|
|
}
|
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
|
|
|
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
|
|
{
|
|
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-03-05 20:18:37 +01:00
|
|
|
public static void EmitVectorBinaryOpByElemSx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
|
|
|
|
|
|
|
|
EmitVectorOpByElem(Context, Emit, Op.Index, false, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorBinaryOpByElemZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
|
|
|
|
|
|
|
|
EmitVectorOpByElem(Context, Emit, Op.Index, false, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorTernaryOpByElemZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
|
|
|
|
|
|
|
|
EmitVectorOpByElem(Context, Emit, Op.Index, true, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorOpByElem(AILEmitterCtx Context, Action Emit, int Elem, bool Ternary, bool Signed)
|
|
|
|
{
|
|
|
|
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
int Bytes = Op.GetBitsCount() >> 3;
|
|
|
|
int Elems = Bytes >> Op.Size;
|
2018-03-05 20:18:37 +01:00
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
2018-03-05 20:18:37 +01:00
|
|
|
{
|
|
|
|
if (Ternary)
|
|
|
|
{
|
|
|
|
EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
|
|
|
|
}
|
|
|
|
|
|
|
|
EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
|
2018-03-16 02:36:47 +01:00
|
|
|
EmitVectorExtract(Context, Op.Rm, Elem, Op.Size, Signed);
|
2018-03-05 20:18:37 +01:00
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
2018-03-16 02:36:47 +01:00
|
|
|
EmitVectorInsertTmp(Context, Index, Op.Size);
|
2018-03-05 20:18:37 +01:00
|
|
|
}
|
|
|
|
|
2018-03-16 02:36:47 +01:00
|
|
|
Context.EmitLdvectmp();
|
|
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
|
2018-03-05 20:18:37 +01:00
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
|
|
{
|
|
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
public static void EmitVectorImmUnaryOp(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorImmOp(Context, Emit, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorImmBinaryOp(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorImmOp(Context, Emit, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorImmOp(AILEmitterCtx Context, Action Emit, bool Binary)
|
|
|
|
{
|
|
|
|
AOpCodeSimdImm Op = (AOpCodeSimdImm)Context.CurrOp;
|
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
int Bytes = Op.GetBitsCount() >> 3;
|
|
|
|
int Elems = Bytes >> Op.Size;
|
2018-02-17 22:06:11 +01:00
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
if (Binary)
|
|
|
|
{
|
|
|
|
EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitLdc_I8(Op.Imm);
|
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
|
|
|
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
|
|
{
|
|
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-20 18:39:03 +01:00
|
|
|
public static void EmitVectorWidenRmBinaryOpSx(AILEmitterCtx Context, Action Emit)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
2018-02-20 18:39:03 +01:00
|
|
|
EmitVectorWidenRmBinaryOp(Context, Emit, true);
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
|
2018-02-20 18:39:03 +01:00
|
|
|
public static void EmitVectorWidenRmBinaryOpZx(AILEmitterCtx Context, Action Emit)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
2018-02-20 18:39:03 +01:00
|
|
|
EmitVectorWidenRmBinaryOp(Context, Emit, false);
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
|
2018-02-20 18:39:03 +01:00
|
|
|
public static void EmitVectorWidenRmBinaryOp(AILEmitterCtx Context, Action Emit, bool Signed)
|
2018-02-17 22:06:11 +01:00
|
|
|
{
|
|
|
|
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
|
|
|
|
|
|
|
int Elems = 8 >> Op.Size;
|
|
|
|
|
|
|
|
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
|
|
|
|
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
|
|
{
|
|
|
|
EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, Signed);
|
|
|
|
EmitVectorExtract(Context, Op.Rm, Part + Index, Op.Size, Signed);
|
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
|
|
|
EmitVectorInsertTmp(Context, Index, Op.Size + 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitLdvectmp();
|
|
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
}
|
|
|
|
|
2018-02-20 18:39:03 +01:00
|
|
|
public static void EmitVectorWidenRnRmBinaryOpSx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
2018-03-07 01:36:49 +01:00
|
|
|
EmitVectorWidenRnRmOp(Context, Emit, false, true);
|
2018-02-20 18:39:03 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorWidenRnRmBinaryOpZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
2018-03-07 01:36:49 +01:00
|
|
|
EmitVectorWidenRnRmOp(Context, Emit, false, false);
|
2018-02-20 18:39:03 +01:00
|
|
|
}
|
|
|
|
|
2018-03-07 01:36:49 +01:00
|
|
|
public static void EmitVectorWidenRnRmTernaryOpSx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorWidenRnRmOp(Context, Emit, true, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorWidenRnRmTernaryOpZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorWidenRnRmOp(Context, Emit, true, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorWidenRnRmOp(AILEmitterCtx Context, Action Emit, bool Ternary, bool Signed)
|
2018-02-20 18:39:03 +01:00
|
|
|
{
|
|
|
|
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
|
|
|
|
|
|
|
int Elems = 8 >> Op.Size;
|
|
|
|
|
|
|
|
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
|
|
|
|
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
|
|
{
|
2018-03-07 01:36:49 +01:00
|
|
|
if (Ternary)
|
|
|
|
{
|
|
|
|
EmitVectorExtract(Context, Op.Rd, Index, Op.Size + 1, Signed);
|
|
|
|
}
|
|
|
|
|
2018-02-20 18:39:03 +01:00
|
|
|
EmitVectorExtract(Context, Op.Rn, Part + Index, Op.Size, Signed);
|
|
|
|
EmitVectorExtract(Context, Op.Rm, Part + Index, Op.Size, Signed);
|
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
|
|
|
EmitVectorInsertTmp(Context, Index, Op.Size + 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitLdvectmp();
|
|
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
}
|
|
|
|
|
2018-07-03 08:31:48 +02:00
|
|
|
public static void EmitVectorPairwiseOpSx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorPairwiseOp(Context, Emit, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorPairwiseOpZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitVectorPairwiseOp(Context, Emit, false);
|
|
|
|
}
|
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
public static void EmitVectorPairwiseOp(AILEmitterCtx Context, Action Emit, bool Signed)
|
2018-07-03 08:31:48 +02:00
|
|
|
{
|
|
|
|
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
int Words = Op.GetBitsCount() >> 4;
|
|
|
|
int Pairs = Words >> Op.Size;
|
2018-07-03 08:31:48 +02:00
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
for (int Index = 0; Index < Pairs; Index++)
|
2018-07-03 08:31:48 +02:00
|
|
|
{
|
2018-07-19 02:06:28 +02:00
|
|
|
int Idx = Index << 1;
|
2018-07-03 08:31:48 +02:00
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
EmitVectorExtract(Context, Op.Rn, Idx, Op.Size, Signed);
|
|
|
|
EmitVectorExtract(Context, Op.Rn, Idx + 1, Op.Size, Signed);
|
2018-07-03 08:31:48 +02:00
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
EmitVectorExtract(Context, Op.Rm, Idx, Op.Size, Signed);
|
|
|
|
EmitVectorExtract(Context, Op.Rm, Idx + 1, Op.Size, Signed);
|
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
|
|
|
EmitVectorInsertTmp(Context, Pairs + Index, Op.Size);
|
|
|
|
EmitVectorInsertTmp(Context, Index, Op.Size);
|
2018-07-03 08:31:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitLdvectmp();
|
|
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
|
|
|
|
if (Op.RegisterSize == ARegisterSize.SIMD64)
|
|
|
|
{
|
|
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
public static void EmitScalarSaturatingNarrowOpSxSx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitSaturatingNarrowOp(Context, Emit, true, true, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitScalarSaturatingNarrowOpSxZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitSaturatingNarrowOp(Context, Emit, true, false, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitScalarSaturatingNarrowOpZxZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitSaturatingNarrowOp(Context, Emit, false, false, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorSaturatingNarrowOpSxSx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitSaturatingNarrowOp(Context, Emit, true, true, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorSaturatingNarrowOpSxZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitSaturatingNarrowOp(Context, Emit, true, false, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorSaturatingNarrowOpZxZx(AILEmitterCtx Context, Action Emit)
|
|
|
|
{
|
|
|
|
EmitSaturatingNarrowOp(Context, Emit, false, false, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitSaturatingNarrowOp(
|
|
|
|
AILEmitterCtx Context,
|
|
|
|
Action Emit,
|
|
|
|
bool SignedSrc,
|
|
|
|
bool SignedDst,
|
|
|
|
bool Scalar)
|
|
|
|
{
|
|
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
|
|
|
|
int Elems = !Scalar ? 8 >> Op.Size : 1;
|
2018-07-15 05:53:26 +02:00
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
int ESize = 8 << Op.Size;
|
|
|
|
|
|
|
|
int Part = !Scalar && (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0;
|
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
long TMaxValue = SignedDst ? (1 << (ESize - 1)) - 1 : (long)(~0UL >> (64 - ESize));
|
2018-07-14 18:13:02 +02:00
|
|
|
long TMinValue = SignedDst ? -((1 << (ESize - 1))) : 0;
|
|
|
|
|
|
|
|
Context.EmitLdc_I8(0L);
|
|
|
|
Context.EmitSttmp();
|
|
|
|
|
2018-07-15 05:53:26 +02:00
|
|
|
if (Part != 0)
|
|
|
|
{
|
|
|
|
Context.EmitLdvec(Op.Rd);
|
|
|
|
Context.EmitStvectmp();
|
|
|
|
}
|
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
|
|
{
|
|
|
|
AILLabel LblLe = new AILLabel();
|
|
|
|
AILLabel LblGeEnd = new AILLabel();
|
|
|
|
|
|
|
|
EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
|
|
|
|
|
|
|
|
Emit();
|
|
|
|
|
|
|
|
Context.Emit(OpCodes.Dup);
|
|
|
|
|
|
|
|
Context.EmitLdc_I8(TMaxValue);
|
|
|
|
|
|
|
|
Context.Emit(SignedSrc ? OpCodes.Ble_S : OpCodes.Ble_Un_S, LblLe);
|
|
|
|
|
|
|
|
Context.Emit(OpCodes.Pop);
|
|
|
|
|
|
|
|
Context.EmitLdc_I8(TMaxValue);
|
|
|
|
Context.EmitLdc_I8(0x8000000L);
|
|
|
|
Context.EmitSttmp();
|
|
|
|
|
|
|
|
Context.Emit(OpCodes.Br_S, LblGeEnd);
|
|
|
|
|
|
|
|
Context.MarkLabel(LblLe);
|
|
|
|
|
|
|
|
Context.Emit(OpCodes.Dup);
|
|
|
|
|
|
|
|
Context.EmitLdc_I8(TMinValue);
|
|
|
|
|
|
|
|
Context.Emit(SignedSrc ? OpCodes.Bge_S : OpCodes.Bge_Un_S, LblGeEnd);
|
|
|
|
|
|
|
|
Context.Emit(OpCodes.Pop);
|
|
|
|
|
|
|
|
Context.EmitLdc_I8(TMinValue);
|
|
|
|
Context.EmitLdc_I8(0x8000000L);
|
|
|
|
Context.EmitSttmp();
|
|
|
|
|
|
|
|
Context.MarkLabel(LblGeEnd);
|
|
|
|
|
|
|
|
if (Scalar)
|
|
|
|
{
|
2018-07-19 02:06:28 +02:00
|
|
|
EmitVectorZeroLowerTmp(Context);
|
2018-07-14 18:13:02 +02:00
|
|
|
}
|
|
|
|
|
2018-07-15 05:53:26 +02:00
|
|
|
EmitVectorInsertTmp(Context, Part + Index, Op.Size);
|
2018-07-14 18:13:02 +02:00
|
|
|
}
|
|
|
|
|
2018-07-15 05:53:26 +02:00
|
|
|
Context.EmitLdvectmp();
|
|
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
|
2018-07-14 18:13:02 +02:00
|
|
|
if (Part == 0)
|
|
|
|
{
|
|
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
|
|
|
|
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
|
|
|
|
Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpsr));
|
|
|
|
Context.EmitLdtmp();
|
|
|
|
Context.Emit(OpCodes.Conv_I4);
|
|
|
|
Context.Emit(OpCodes.Or);
|
|
|
|
Context.EmitCallPropSet(typeof(AThreadState), nameof(AThreadState.Fpsr));
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
public static void EmitScalarSet(AILEmitterCtx Context, int Reg, int Size)
|
|
|
|
{
|
|
|
|
EmitVectorZeroAll(Context, Reg);
|
|
|
|
EmitVectorInsert(Context, Reg, 0, Size);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitScalarSetF(AILEmitterCtx Context, int Reg, int Size)
|
|
|
|
{
|
|
|
|
EmitVectorZeroAll(Context, Reg);
|
|
|
|
EmitVectorInsertF(Context, Reg, 0, Size);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorExtractSx(AILEmitterCtx Context, int Reg, int Index, int Size)
|
|
|
|
{
|
|
|
|
EmitVectorExtract(Context, Reg, Index, Size, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorExtractZx(AILEmitterCtx Context, int Reg, int Index, int Size)
|
|
|
|
{
|
|
|
|
EmitVectorExtract(Context, Reg, Index, Size, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorExtract(AILEmitterCtx Context, int Reg, int Index, int Size, bool Signed)
|
|
|
|
{
|
2018-04-06 20:39:39 +02:00
|
|
|
ThrowIfInvalid(Index, Size);
|
2018-02-17 22:06:11 +01:00
|
|
|
|
|
|
|
IAOpCodeSimd Op = (IAOpCodeSimd)Context.CurrOp;
|
|
|
|
|
|
|
|
Context.EmitLdvec(Reg);
|
|
|
|
Context.EmitLdc_I4(Index);
|
|
|
|
Context.EmitLdc_I4(Size);
|
|
|
|
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, Signed
|
|
|
|
? nameof(AVectorHelper.VectorExtractIntSx)
|
|
|
|
: nameof(AVectorHelper.VectorExtractIntZx));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorExtractF(AILEmitterCtx Context, int Reg, int Index, int Size)
|
|
|
|
{
|
2018-04-06 20:39:39 +02:00
|
|
|
ThrowIfInvalidF(Index, Size);
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
Context.EmitLdvec(Reg);
|
|
|
|
Context.EmitLdc_I4(Index);
|
|
|
|
|
|
|
|
if (Size == 0)
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorExtractSingle));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else if (Size == 1)
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorExtractDouble));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorZeroAll(AILEmitterCtx Context, int Rd)
|
|
|
|
{
|
|
|
|
EmitVectorZeroLower(Context, Rd);
|
|
|
|
EmitVectorZeroUpper(Context, Rd);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorZeroLower(AILEmitterCtx Context, int Rd)
|
|
|
|
{
|
|
|
|
EmitVectorInsert(Context, Rd, 0, 3, 0);
|
|
|
|
}
|
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
public static void EmitVectorZeroLowerTmp(AILEmitterCtx Context)
|
|
|
|
{
|
|
|
|
EmitVectorInsertTmp(Context, 0, 3, 0);
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
public static void EmitVectorZeroUpper(AILEmitterCtx Context, int Rd)
|
|
|
|
{
|
|
|
|
EmitVectorInsert(Context, Rd, 1, 3, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size)
|
|
|
|
{
|
2018-04-06 20:39:39 +02:00
|
|
|
ThrowIfInvalid(Index, Size);
|
2018-02-17 22:06:11 +01:00
|
|
|
|
|
|
|
Context.EmitLdvec(Reg);
|
|
|
|
Context.EmitLdc_I4(Index);
|
|
|
|
Context.EmitLdc_I4(Size);
|
|
|
|
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInsertInt));
|
2018-02-17 22:06:11 +01:00
|
|
|
|
|
|
|
Context.EmitStvec(Reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorInsertTmp(AILEmitterCtx Context, int Index, int Size)
|
|
|
|
{
|
2018-04-06 20:39:39 +02:00
|
|
|
ThrowIfInvalid(Index, Size);
|
2018-02-17 22:06:11 +01:00
|
|
|
|
|
|
|
Context.EmitLdvectmp();
|
|
|
|
Context.EmitLdc_I4(Index);
|
|
|
|
Context.EmitLdc_I4(Size);
|
|
|
|
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInsertInt));
|
2018-02-17 22:06:11 +01:00
|
|
|
|
|
|
|
Context.EmitStvectmp();
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size, long Value)
|
|
|
|
{
|
2018-04-06 20:39:39 +02:00
|
|
|
ThrowIfInvalid(Index, Size);
|
2018-02-17 22:06:11 +01:00
|
|
|
|
|
|
|
Context.EmitLdc_I8(Value);
|
|
|
|
Context.EmitLdvec(Reg);
|
|
|
|
Context.EmitLdc_I4(Index);
|
|
|
|
Context.EmitLdc_I4(Size);
|
|
|
|
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInsertInt));
|
2018-02-17 22:06:11 +01:00
|
|
|
|
|
|
|
Context.EmitStvec(Reg);
|
|
|
|
}
|
|
|
|
|
2018-07-19 02:06:28 +02:00
|
|
|
public static void EmitVectorInsertTmp(AILEmitterCtx Context, int Index, int Size, long Value)
|
|
|
|
{
|
|
|
|
ThrowIfInvalid(Index, Size);
|
|
|
|
|
|
|
|
Context.EmitLdc_I8(Value);
|
|
|
|
Context.EmitLdvectmp();
|
|
|
|
Context.EmitLdc_I4(Index);
|
|
|
|
Context.EmitLdc_I4(Size);
|
|
|
|
|
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInsertInt));
|
|
|
|
|
|
|
|
Context.EmitStvectmp();
|
|
|
|
}
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
public static void EmitVectorInsertF(AILEmitterCtx Context, int Reg, int Index, int Size)
|
|
|
|
{
|
2018-04-06 20:39:39 +02:00
|
|
|
ThrowIfInvalidF(Index, Size);
|
|
|
|
|
2018-02-17 22:06:11 +01:00
|
|
|
Context.EmitLdvec(Reg);
|
|
|
|
Context.EmitLdc_I4(Index);
|
|
|
|
|
|
|
|
if (Size == 0)
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInsertSingle));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else if (Size == 1)
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInsertDouble));
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitStvec(Reg);
|
|
|
|
}
|
2018-02-18 05:57:33 +01:00
|
|
|
|
|
|
|
public static void EmitVectorInsertTmpF(AILEmitterCtx Context, int Index, int Size)
|
|
|
|
{
|
2018-04-06 20:39:39 +02:00
|
|
|
ThrowIfInvalidF(Index, Size);
|
|
|
|
|
2018-02-18 05:57:33 +01:00
|
|
|
Context.EmitLdvectmp();
|
|
|
|
Context.EmitLdc_I4(Index);
|
|
|
|
|
|
|
|
if (Size == 0)
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInsertSingle));
|
2018-02-18 05:57:33 +01:00
|
|
|
}
|
|
|
|
else if (Size == 1)
|
|
|
|
{
|
2018-05-12 01:10:27 +02:00
|
|
|
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInsertDouble));
|
2018-02-18 05:57:33 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
|
|
}
|
|
|
|
|
|
|
|
Context.EmitStvectmp();
|
|
|
|
}
|
2018-04-06 20:39:39 +02:00
|
|
|
|
|
|
|
private static void ThrowIfInvalid(int Index, int Size)
|
|
|
|
{
|
|
|
|
if ((uint)Size > 3)
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((uint)Index >= 16 >> Size)
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(Index));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void ThrowIfInvalidF(int Index, int Size)
|
|
|
|
{
|
|
|
|
if ((uint)Size > 1)
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(Size));
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((uint)Index >= 4 >> Size)
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(Index));
|
|
|
|
}
|
|
|
|
}
|
2018-02-17 22:06:11 +01:00
|
|
|
}
|
2018-04-08 21:08:57 +02:00
|
|
|
}
|