mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-07-14 13:46:15 +02:00
Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed box). (#352)
* Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update Pseudocode.cs * Update Instructions.cs * Update Bits.cs * Update Integer.cs * Update AOpCodeTable.cs * Create AInstEmitSimdHash.cs * Update ASoftFallback.cs
This commit is contained in:
LDj3SNuD
gdkchan
parent
521751795a
commit
34100051e4
|
|
@ -366,6 +366,10 @@ namespace ChocolArm64
|
|||
SetA64("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt));
|
||||
SetA64("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd));
|
||||
SetA64("0x0011100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_V, typeof(AOpCodeSimd));
|
||||
SetA64("01011110000xxxxx010000xxxxxxxxxx", AInstEmit.Sha256h_V, typeof(AOpCodeSimdReg));
|
||||
SetA64("01011110000xxxxx010100xxxxxxxxxx", AInstEmit.Sha256h2_V, typeof(AOpCodeSimdReg));
|
||||
SetA64("0101111000101000001010xxxxxxxxxx", AInstEmit.Sha256su0_V, typeof(AOpCodeSimd));
|
||||
SetA64("01011110000xxxxx011000xxxxxxxxxx", AInstEmit.Sha256su1_V, typeof(AOpCodeSimdReg));
|
||||
SetA64("010111110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_S, typeof(AOpCodeSimdShImm));
|
||||
SetA64("0x0011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
|
||||
SetA64("0x101110<<100001001110xxxxxxxxxx", AInstEmit.Shll_V, typeof(AOpCodeSimd));
|
||||
|
|
|
|||
61
ChocolArm64/Instruction/AInstEmitSimdHash.cs
Normal file
61
ChocolArm64/Instruction/AInstEmitSimdHash.cs
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
using ChocolArm64.Decoder;
|
||||
using ChocolArm64.Translation;
|
||||
|
||||
namespace ChocolArm64.Instruction
|
||||
{
|
||||
static partial class AInstEmit
|
||||
{
|
||||
#region "Sha256"
|
||||
public static void Sha256h_V(AILEmitterCtx Context)
|
||||
{
|
||||
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
||||
|
||||
Context.EmitLdvec(Op.Rd);
|
||||
Context.EmitLdvec(Op.Rn);
|
||||
Context.EmitLdvec(Op.Rm);
|
||||
|
||||
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashLower));
|
||||
|
||||
Context.EmitStvec(Op.Rd);
|
||||
}
|
||||
|
||||
public static void Sha256h2_V(AILEmitterCtx Context)
|
||||
{
|
||||
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
||||
|
||||
Context.EmitLdvec(Op.Rd);
|
||||
Context.EmitLdvec(Op.Rn);
|
||||
Context.EmitLdvec(Op.Rm);
|
||||
|
||||
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashUpper));
|
||||
|
||||
Context.EmitStvec(Op.Rd);
|
||||
}
|
||||
|
||||
public static void Sha256su0_V(AILEmitterCtx Context)
|
||||
{
|
||||
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
||||
|
||||
Context.EmitLdvec(Op.Rd);
|
||||
Context.EmitLdvec(Op.Rn);
|
||||
|
||||
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.SchedulePart1));
|
||||
|
||||
Context.EmitStvec(Op.Rd);
|
||||
}
|
||||
|
||||
public static void Sha256su1_V(AILEmitterCtx Context)
|
||||
{
|
||||
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
||||
|
||||
Context.EmitLdvec(Op.Rd);
|
||||
Context.EmitLdvec(Op.Rn);
|
||||
Context.EmitLdvec(Op.Rm);
|
||||
|
||||
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.SchedulePart2));
|
||||
|
||||
Context.EmitStvec(Op.Rd);
|
||||
}
|
||||
#endregion
|
||||
}
|
||||
}
|
||||
|
|
@ -1,9 +1,14 @@
|
|||
using ChocolArm64.State;
|
||||
using ChocolArm64.Translation;
|
||||
using System;
|
||||
using System.Runtime.CompilerServices;
|
||||
using System.Runtime.Intrinsics;
|
||||
using System.Runtime.Intrinsics.X86;
|
||||
|
||||
namespace ChocolArm64.Instruction
|
||||
{
|
||||
using static AVectorHelper;
|
||||
|
||||
static class ASoftFallback
|
||||
{
|
||||
public static void EmitCall(AILEmitterCtx Context, string MthdName)
|
||||
|
|
@ -405,6 +410,154 @@ namespace ChocolArm64.Instruction
|
|||
}
|
||||
#endregion
|
||||
|
||||
#region "Sha256"
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
public static Vector128<float> HashLower(Vector128<float> hash_abcd, Vector128<float> hash_efgh, Vector128<float> wk)
|
||||
{
|
||||
return SHA256hash(hash_abcd, hash_efgh, wk, true);
|
||||
}
|
||||
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
public static Vector128<float> HashUpper(Vector128<float> hash_efgh, Vector128<float> hash_abcd, Vector128<float> wk)
|
||||
{
|
||||
return SHA256hash(hash_abcd, hash_efgh, wk, false);
|
||||
}
|
||||
|
||||
public static Vector128<float> SchedulePart1(Vector128<float> w0_3, Vector128<float> w4_7)
|
||||
{
|
||||
Vector128<float> result = new Vector128<float>();
|
||||
|
||||
for (int e = 0; e <= 3; e++)
|
||||
{
|
||||
uint elt = (uint)VectorExtractIntZx(e <= 2 ? w0_3 : w4_7, (byte)(e <= 2 ? e + 1 : 0), 2);
|
||||
|
||||
elt = elt.Ror(7) ^ elt.Ror(18) ^ elt.Lsr(3);
|
||||
|
||||
elt += (uint)VectorExtractIntZx(w0_3, (byte)e, 2);
|
||||
|
||||
result = VectorInsertInt((ulong)elt, result, (byte)e, 2);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
public static Vector128<float> SchedulePart2(Vector128<float> w0_3, Vector128<float> w8_11, Vector128<float> w12_15)
|
||||
{
|
||||
Vector128<float> result = new Vector128<float>();
|
||||
|
||||
ulong T1 = VectorExtractIntZx(w12_15, (byte)1, 3);
|
||||
|
||||
for (int e = 0; e <= 1; e++)
|
||||
{
|
||||
uint elt = T1.ULongPart(e);
|
||||
|
||||
elt = elt.Ror(17) ^ elt.Ror(19) ^ elt.Lsr(10);
|
||||
|
||||
elt += (uint)VectorExtractIntZx(w0_3, (byte)e, 2);
|
||||
elt += (uint)VectorExtractIntZx(w8_11, (byte)(e + 1), 2);
|
||||
|
||||
result = VectorInsertInt((ulong)elt, result, (byte)e, 2);
|
||||
}
|
||||
|
||||
T1 = VectorExtractIntZx(result, (byte)0, 3);
|
||||
|
||||
for (int e = 2; e <= 3; e++)
|
||||
{
|
||||
uint elt = T1.ULongPart(e - 2);
|
||||
|
||||
elt = elt.Ror(17) ^ elt.Ror(19) ^ elt.Lsr(10);
|
||||
|
||||
elt += (uint)VectorExtractIntZx(w0_3, (byte)e, 2);
|
||||
elt += (uint)VectorExtractIntZx(e == 2 ? w8_11 : w12_15, (byte)(e == 2 ? 3 : 0), 2);
|
||||
|
||||
result = VectorInsertInt((ulong)elt, result, (byte)e, 2);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
private static Vector128<float> SHA256hash(Vector128<float> X, Vector128<float> Y, Vector128<float> W, bool part1)
|
||||
{
|
||||
for (int e = 0; e <= 3; e++)
|
||||
{
|
||||
uint chs = SHAchoose((uint)VectorExtractIntZx(Y, (byte)0, 2),
|
||||
(uint)VectorExtractIntZx(Y, (byte)1, 2),
|
||||
(uint)VectorExtractIntZx(Y, (byte)2, 2));
|
||||
|
||||
uint maj = SHAmajority((uint)VectorExtractIntZx(X, (byte)0, 2),
|
||||
(uint)VectorExtractIntZx(X, (byte)1, 2),
|
||||
(uint)VectorExtractIntZx(X, (byte)2, 2));
|
||||
|
||||
uint t1 = (uint)VectorExtractIntZx(Y, (byte)3, 2);
|
||||
t1 += SHAhashSIGMA1((uint)VectorExtractIntZx(Y, (byte)0, 2)) + chs;
|
||||
t1 += (uint)VectorExtractIntZx(W, (byte)e, 2);
|
||||
|
||||
uint t2 = t1 + (uint)VectorExtractIntZx(X, (byte)3, 2);
|
||||
X = VectorInsertInt((ulong)t2, X, (byte)3, 2);
|
||||
t2 = t1 + SHAhashSIGMA0((uint)VectorExtractIntZx(X, (byte)0, 2)) + maj;
|
||||
Y = VectorInsertInt((ulong)t2, Y, (byte)3, 2);
|
||||
|
||||
Rol32_256(ref Y, ref X);
|
||||
}
|
||||
|
||||
return part1 ? X : Y;
|
||||
}
|
||||
|
||||
private static void Rol32_256(ref Vector128<float> Y, ref Vector128<float> X)
|
||||
{
|
||||
if (!Sse2.IsSupported)
|
||||
{
|
||||
throw new PlatformNotSupportedException();
|
||||
}
|
||||
|
||||
uint yE3 = (uint)VectorExtractIntZx(Y, (byte)3, 2);
|
||||
uint xE3 = (uint)VectorExtractIntZx(X, (byte)3, 2);
|
||||
|
||||
Y = Sse.StaticCast<uint, float>(Sse2.ShiftLeftLogical128BitLane(Sse.StaticCast<float, uint>(Y), (byte)4));
|
||||
X = Sse.StaticCast<uint, float>(Sse2.ShiftLeftLogical128BitLane(Sse.StaticCast<float, uint>(X), (byte)4));
|
||||
|
||||
Y = VectorInsertInt((ulong)xE3, Y, (byte)0, 2);
|
||||
X = VectorInsertInt((ulong)yE3, X, (byte)0, 2);
|
||||
}
|
||||
|
||||
private static uint SHAhashSIGMA0(uint x)
|
||||
{
|
||||
return x.Ror(2) ^ x.Ror(13) ^ x.Ror(22);
|
||||
}
|
||||
|
||||
private static uint SHAhashSIGMA1(uint x)
|
||||
{
|
||||
return x.Ror(6) ^ x.Ror(11) ^ x.Ror(25);
|
||||
}
|
||||
|
||||
private static uint SHAmajority(uint x, uint y, uint z)
|
||||
{
|
||||
return (x & y) | ((x | y) & z);
|
||||
}
|
||||
|
||||
private static uint SHAchoose(uint x, uint y, uint z)
|
||||
{
|
||||
return ((y ^ z) & x) ^ z;
|
||||
}
|
||||
|
||||
private static uint Ror(this uint value, int count)
|
||||
{
|
||||
return (value >> count) | (value << (32 - count));
|
||||
}
|
||||
|
||||
private static uint Lsr(this uint value, int count)
|
||||
{
|
||||
return value >> count;
|
||||
}
|
||||
|
||||
private static uint ULongPart(this ulong value, int part)
|
||||
{
|
||||
return part == 0
|
||||
? (uint)(value & 0xFFFFFFFFUL)
|
||||
: (uint)(value >> 32);
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region "Reverse"
|
||||
public static uint ReverseBits8(uint Value)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1245,6 +1245,36 @@ namespace Ryujinx.Tests.Cpu
|
|||
});
|
||||
}
|
||||
|
||||
[Test, Explicit, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")] // 1250 tests.
|
||||
public void Sha256su0_V([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Random(5)] ulong Z0, [Random(5)] ulong Z1,
|
||||
[Random(5)] ulong A0, [Random(5)] ulong A1)
|
||||
{
|
||||
uint Opcode = 0x5E282800; // SHA256SU0 V0.4S, V0.4S
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z0, Z1);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1));
|
||||
AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1));
|
||||
SimdFp.Sha256su0_V(Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("SQABS <V><d>, <V><n>")]
|
||||
public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
|
|
|
|||
|
|
@ -1747,6 +1747,117 @@ namespace Ryujinx.Tests.Cpu
|
|||
});
|
||||
}
|
||||
|
||||
[Test, Explicit, Description("SHA256H <Qd>, <Qn>, <Vm>.4S")] // 2916 tests.
|
||||
public void Sha256h_V([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[Random(3)] ulong Z0, [Random(3)] ulong Z1,
|
||||
[Random(3)] ulong A0, [Random(3)] ulong A1,
|
||||
[Random(3)] ulong B0, [Random(3)] ulong B1)
|
||||
{
|
||||
uint Opcode = 0x5E004000; // SHA256H Q0, Q0, V0.4S
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z0, Z1);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1));
|
||||
AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1));
|
||||
AArch64.Vpart(2, 0, new Bits(B0)); AArch64.Vpart(2, 1, new Bits(B1));
|
||||
SimdFp.Sha256h_V(Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
|
||||
Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64()));
|
||||
});
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Explicit, Description("SHA256H2 <Qd>, <Qn>, <Vm>.4S")] // 2916 tests.
|
||||
public void Sha256h2_V([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[Random(3)] ulong Z0, [Random(3)] ulong Z1,
|
||||
[Random(3)] ulong A0, [Random(3)] ulong A1,
|
||||
[Random(3)] ulong B0, [Random(3)] ulong B1)
|
||||
{
|
||||
uint Opcode = 0x5E005000; // SHA256H2 Q0, Q0, V0.4S
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z0, Z1);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1));
|
||||
AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1));
|
||||
AArch64.Vpart(2, 0, new Bits(B0)); AArch64.Vpart(2, 1, new Bits(B1));
|
||||
SimdFp.Sha256h2_V(Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
|
||||
Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64()));
|
||||
});
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Explicit, Description("SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S")] // 2916 tests.
|
||||
public void Sha256su1_V([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[Random(3)] ulong Z0, [Random(3)] ulong Z1,
|
||||
[Random(3)] ulong A0, [Random(3)] ulong A1,
|
||||
[Random(3)] ulong B0, [Random(3)] ulong B1)
|
||||
{
|
||||
uint Opcode = 0x5E006000; // SHA256SU1 V0.4S, V0.4S, V0.4S
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z0, Z1);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1));
|
||||
AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1));
|
||||
AArch64.Vpart(2, 0, new Bits(B0)); AArch64.Vpart(2, 1, new Bits(B1));
|
||||
SimdFp.Sha256su1_V(Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64()));
|
||||
|
||||
Assert.That(GetVectorE0(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQADD <V><d>, <V><n>, <V><m>")]
|
||||
public void Sqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
|
|
|
|||
|
|
@ -3144,6 +3144,34 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// sha256su0_advsimd.html
|
||||
public static void Sha256su0_V(Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if !HaveCryptoExt() then UnallocatedEncoding(); */
|
||||
|
||||
/* Operation */
|
||||
/* CheckCryptoEnabled64(); */
|
||||
|
||||
Bits result = new Bits(128);
|
||||
Bits operand1 = V(128, d);
|
||||
Bits operand2 = V(128, n);
|
||||
Bits T = Bits.Concat(operand2[31, 0], operand1[127, 32]); // bits(128)
|
||||
Bits elt; // bits(32)
|
||||
|
||||
for (int e = 0; e <= 3; e++)
|
||||
{
|
||||
elt = Elem(T, e, 32);
|
||||
elt = EOR(EOR(ROR(elt, 7), ROR(elt, 18)), LSR(elt, 3));
|
||||
Elem(result, e, 32, elt + Elem(operand1, e, 32));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqabs_advsimd.html#SQABS_asisdmisc_R
|
||||
public static void Sqabs_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
@ -5145,6 +5173,84 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// sha256h_advsimd.html
|
||||
public static void Sha256h_V(Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if !HaveCryptoExt() then UnallocatedEncoding(); */
|
||||
|
||||
/* Operation */
|
||||
/* CheckCryptoEnabled64(); */
|
||||
|
||||
Bits result = SHA256hash(V(128, d), V(128, n), V(128, m), true);
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sha256h2_advsimd.html
|
||||
public static void Sha256h2_V(Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if !HaveCryptoExt() then UnallocatedEncoding(); */
|
||||
|
||||
/* Operation */
|
||||
/* CheckCryptoEnabled64(); */
|
||||
|
||||
Bits result = SHA256hash(V(128, n), V(128, d), V(128, m), false);
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sha256su1_advsimd.html
|
||||
public static void Sha256su1_V(Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if !HaveCryptoExt() then UnallocatedEncoding(); */
|
||||
|
||||
/* Operation */
|
||||
/* CheckCryptoEnabled64(); */
|
||||
|
||||
Bits result = new Bits(128);
|
||||
Bits operand1 = V(128, d);
|
||||
Bits operand2 = V(128, n);
|
||||
Bits operand3 = V(128, m);
|
||||
Bits T0 = Bits.Concat(operand3[31, 0], operand2[127, 32]); // bits(128)
|
||||
Bits T1; // bits(64)
|
||||
Bits elt; // bits(32)
|
||||
|
||||
T1 = operand3[127, 64];
|
||||
for (int e = 0; e <= 1; e++)
|
||||
{
|
||||
elt = Elem(T1, e, 32);
|
||||
elt = EOR(EOR(ROR(elt, 17), ROR(elt, 19)), LSR(elt, 10));
|
||||
elt = elt + Elem(operand1, e, 32) + Elem(T0, e, 32);
|
||||
Elem(result, e, 32, elt);
|
||||
}
|
||||
|
||||
T1 = result[63, 0];
|
||||
for (int e = 2; e <= 3; e++)
|
||||
{
|
||||
elt = Elem(T1, e - 2, 32);
|
||||
elt = EOR(EOR(ROR(elt, 17), ROR(elt, 19)), LSR(elt, 10));
|
||||
elt = elt + Elem(operand1, e, 32) + Elem(T0, e, 32);
|
||||
Elem(result, e, 32, elt);
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqadd_advsimd.html#SQADD_asisdsame_only
|
||||
public static void Sqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -469,7 +469,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
if (N == esize)
|
||||
{
|
||||
return new Bits(input);
|
||||
return new Bits(input); // Clone.
|
||||
}
|
||||
|
||||
half = N / 2;
|
||||
|
|
@ -556,7 +556,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
if (shift == 0)
|
||||
{
|
||||
result = new Bits(x);
|
||||
result = new Bits(x); // Clone.
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -720,7 +720,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
if (shift == 0)
|
||||
{
|
||||
result = new Bits(x);
|
||||
result = new Bits(x); // Clone.
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -755,7 +755,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
if (shift == 0)
|
||||
{
|
||||
result = new Bits(x);
|
||||
result = new Bits(x); // Clone.
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -826,7 +826,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
if (shift == 0)
|
||||
{
|
||||
result = new Bits(x);
|
||||
result = new Bits(x); // Clone.
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1008,7 +1008,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
/* assert N > 32; */
|
||||
|
||||
Bits data = new Bits(_data);
|
||||
Bits data = new Bits(_data); // Clone.
|
||||
|
||||
for (int i = N - 1; i >= 32; i--)
|
||||
{
|
||||
|
|
@ -1022,6 +1022,75 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
}
|
||||
#endregion
|
||||
|
||||
#region "functions/crypto/"
|
||||
// shared_pseudocode.html#impl-shared.ROL.2
|
||||
public static Bits ROL(Bits x, int shift)
|
||||
{
|
||||
int N = x.Count;
|
||||
|
||||
/* assert shift >= 0 && shift <= N; */
|
||||
|
||||
if (shift == 0)
|
||||
{
|
||||
return new Bits(x); // Clone.
|
||||
}
|
||||
|
||||
return ROR(x, N - shift);
|
||||
}
|
||||
|
||||
// shared_pseudocode.html#impl-shared.SHA256hash.4
|
||||
public static Bits SHA256hash(Bits _X, Bits _Y, Bits W, bool part1)
|
||||
{
|
||||
Bits X = new Bits(_X); // Clone.
|
||||
Bits Y = new Bits(_Y); // Clone.
|
||||
|
||||
Bits chs, maj, t; // bits(32)
|
||||
|
||||
for (int e = 0; e <= 3; e++)
|
||||
{
|
||||
chs = SHAchoose(Y[31, 0], Y[63, 32], Y[95, 64]);
|
||||
maj = SHAmajority(X[31, 0], X[63, 32], X[95, 64]);
|
||||
|
||||
t = Y[127, 96] + SHAhashSIGMA1(Y[31, 0]) + chs + Elem(W, e, 32);
|
||||
|
||||
X[127, 96] = t + X[127, 96];
|
||||
Y[127, 96] = t + SHAhashSIGMA0(X[31, 0]) + maj;
|
||||
|
||||
// TODO: Implement ASL: "<,>" as C#: "Bits.Split()".
|
||||
/* <Y, X> = ROL(Y : X, 32); */
|
||||
Bits YX = ROL(Bits.Concat(Y, X), 32);
|
||||
Y = YX[255, 128];
|
||||
X = YX[127, 0];
|
||||
}
|
||||
|
||||
return (part1 ? X : Y);
|
||||
}
|
||||
|
||||
// shared_pseudocode.html#impl-shared.SHAchoose.3
|
||||
public static Bits SHAchoose(Bits x, Bits y, Bits z)
|
||||
{
|
||||
return EOR(AND(EOR(y, z), x), z);
|
||||
}
|
||||
|
||||
// shared_pseudocode.html#impl-shared.SHAhashSIGMA0.1
|
||||
public static Bits SHAhashSIGMA0(Bits x)
|
||||
{
|
||||
return EOR(EOR(ROR(x, 2), ROR(x, 13)), ROR(x, 22));
|
||||
}
|
||||
|
||||
// shared_pseudocode.html#impl-shared.SHAhashSIGMA1.1
|
||||
public static Bits SHAhashSIGMA1(Bits x)
|
||||
{
|
||||
return EOR(EOR(ROR(x, 6), ROR(x, 11)), ROR(x, 25));
|
||||
}
|
||||
|
||||
// shared_pseudocode.html#impl-shared.SHAmajority.3
|
||||
public static Bits SHAmajority(Bits x, Bits y, Bits z)
|
||||
{
|
||||
return OR(AND(x, y), AND(OR(x, y), z));
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region "functions/integer/"
|
||||
/* shared_pseudocode.html#impl-shared.AddWithCarry.3 */
|
||||
public static (Bits, Bits) AddWithCarry(int N, Bits x, Bits y, bool carry_in)
|
||||
|
|
|
|||
|
|
@ -14,14 +14,13 @@ namespace Ryujinx.Tests.Cpu.Tester.Types
|
|||
|
||||
public Bits(bool[] values) => bits = new BitArray(values);
|
||||
public Bits(byte[] bytes) => bits = new BitArray(bytes);
|
||||
public Bits(Bits bits) => this.bits = new BitArray(bits.bits);
|
||||
public Bits(Bits bits) => this.bits = new BitArray(bits.bits); // Clone: deep copy.
|
||||
public Bits(int length) => bits = new BitArray(length);
|
||||
public Bits(int length, bool defaultValue) => bits = new BitArray(length, defaultValue);
|
||||
private Bits(BitArray bitArray) => bits = new BitArray(bitArray);
|
||||
public Bits(ulong value) => bits = new BitArray(BitConverter.GetBytes(value));
|
||||
public Bits(uint value) => bits = new BitArray(BitConverter.GetBytes(value));
|
||||
public Bits(ushort value) => bits = new BitArray(BitConverter.GetBytes(value));
|
||||
public Bits(byte value) => bits = new BitArray(new byte[1] {value});
|
||||
public Bits(BigInteger value) => bits = new BitArray(value.ToByteArray());
|
||||
|
||||
private BitArray ToBitArray() => new BitArray(bits);
|
||||
public ulong ToUInt64()
|
||||
|
|
@ -40,21 +39,21 @@ namespace Ryujinx.Tests.Cpu.Tester.Types
|
|||
|
||||
return BitConverter.ToUInt32(dst, 0);
|
||||
}
|
||||
public ushort ToUInt16()
|
||||
public BigInteger ToBigInteger()
|
||||
{
|
||||
byte[] dst = new byte[2];
|
||||
if (bits.Count != 64 &&
|
||||
bits.Count != 32 &&
|
||||
bits.Count != 16 &&
|
||||
bits.Count != 8)
|
||||
{
|
||||
throw new InvalidOperationException();
|
||||
}
|
||||
|
||||
byte[] dst = new byte[bits.Count / 8];
|
||||
|
||||
bits.CopyTo(dst, 0);
|
||||
|
||||
return BitConverter.ToUInt16(dst, 0);
|
||||
}
|
||||
public byte ToByte()
|
||||
{
|
||||
byte[] dst = new byte[1];
|
||||
|
||||
bits.CopyTo(dst, 0);
|
||||
|
||||
return dst[0];
|
||||
return new BigInteger(dst);
|
||||
}
|
||||
|
||||
public bool this[int index] // ASL: "<>".
|
||||
|
|
@ -101,7 +100,7 @@ namespace Ryujinx.Tests.Cpu.Tester.Types
|
|||
}
|
||||
|
||||
public bool IsReadOnly { get => false; } // Mutable.
|
||||
public int Count { get => bits.Count; }
|
||||
public int Count { get => bits.Count; } // Not resizable.
|
||||
public bool IsSynchronized { get => bits.IsSynchronized; }
|
||||
public object SyncRoot { get => bits.SyncRoot; }
|
||||
public Bits And(Bits value) => new Bits(new BitArray(this.bits).And(value.bits)); // Immutable.
|
||||
|
|
@ -180,17 +179,7 @@ namespace Ryujinx.Tests.Cpu.Tester.Types
|
|||
throw new ArgumentNullException();
|
||||
}
|
||||
|
||||
BigInteger dst;
|
||||
|
||||
switch (left.Count)
|
||||
{
|
||||
case 8: dst = left.ToByte() + right; break;
|
||||
case 16: dst = left.ToUInt16() + right; break;
|
||||
case 32: dst = left.ToUInt32() + right; break;
|
||||
case 64: dst = left.ToUInt64() + right; break;
|
||||
|
||||
default: throw new ArgumentOutOfRangeException();
|
||||
}
|
||||
BigInteger dst = left.ToBigInteger() + right;
|
||||
|
||||
return dst.SubBigInteger(left.Count - 1, 0);
|
||||
}
|
||||
|
|
@ -203,20 +192,10 @@ namespace Ryujinx.Tests.Cpu.Tester.Types
|
|||
|
||||
if (left.Count != right.Count)
|
||||
{
|
||||
throw new ArgumentException();
|
||||
throw new InvalidOperationException();
|
||||
}
|
||||
|
||||
BigInteger dst;
|
||||
|
||||
switch (left.Count)
|
||||
{
|
||||
case 8: dst = left.ToByte() + (BigInteger)right.ToByte(); break;
|
||||
case 16: dst = left.ToUInt16() + (BigInteger)right.ToUInt16(); break;
|
||||
case 32: dst = left.ToUInt32() + (BigInteger)right.ToUInt32(); break;
|
||||
case 64: dst = left.ToUInt64() + (BigInteger)right.ToUInt64(); break;
|
||||
|
||||
default: throw new ArgumentOutOfRangeException();
|
||||
}
|
||||
BigInteger dst = left.ToBigInteger() + right.ToBigInteger();
|
||||
|
||||
return dst.SubBigInteger(left.Count - 1, 0);
|
||||
}
|
||||
|
|
@ -229,20 +208,10 @@ namespace Ryujinx.Tests.Cpu.Tester.Types
|
|||
|
||||
if (left.Count != right.Count)
|
||||
{
|
||||
throw new ArgumentException();
|
||||
throw new InvalidOperationException();
|
||||
}
|
||||
|
||||
BigInteger dst;
|
||||
|
||||
switch (left.Count)
|
||||
{
|
||||
case 8: dst = left.ToByte() - (BigInteger)right.ToByte(); break;
|
||||
case 16: dst = left.ToUInt16() - (BigInteger)right.ToUInt16(); break;
|
||||
case 32: dst = left.ToUInt32() - (BigInteger)right.ToUInt32(); break;
|
||||
case 64: dst = left.ToUInt64() - (BigInteger)right.ToUInt64(); break;
|
||||
|
||||
default: throw new ArgumentOutOfRangeException();
|
||||
}
|
||||
BigInteger dst = left.ToBigInteger() - right.ToBigInteger();
|
||||
|
||||
return dst.SubBigInteger(left.Count - 1, 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ namespace Ryujinx.Tests.Cpu.Tester.Types
|
|||
throw new IndexOutOfRangeException();
|
||||
}
|
||||
|
||||
Bits src = new Bits(x.ToByteArray());
|
||||
Bits src = new Bits(x);
|
||||
bool[] dst = new bool[highIndex - lowIndex + 1];
|
||||
|
||||
for (int i = lowIndex, n = 0; i <= highIndex; i++, n++)
|
||||
|
|
|
|||
Loading…
Reference in a new issue