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https://github.com/Ryujinx/Ryujinx.git
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ARMeilleure: Add gfni
acceleration (#3669)
* ARMeilleure: Add `GFNI` detection This is intended for utilizing the `gf2p8affineqb` instruction * ARMeilleure: Add `gf2p8affineqb` Not using the VEX or EVEX-form of this instruction is intentional. There are `GFNI`-chips that do not support AVX(so no VEX encoding) such as Tremont(Lakefield) chips as well as Jasper Lake.13df339fe7/GenuineIntel/GenuineIntel00806A1_Lakefield_LC_InstLatX64.txt (L1297-L1299)
13df339fe7/GenuineIntel/GenuineIntel00906C0_JasperLake_InstLatX64.txt (L1252-L1254)
* ARMeilleure: Add `gfni` acceleration of `Rbit_V` Passes all `Rbit_V*` unit tests on my `i9-11900k` * ARMeilleure: Add `gfni` acceleration of `S{l,r}i_V` Also added a fast-path for when the shift amount is greater than the size of the element. * ARMeilleure: Add `gfni` acceleration of `Shl_V` and `Sshr_V` * ARMeilleure: Increment InternalVersion * ARMeilleure: Fix Intrinsic and Assembler Table alignment `gf2p8affineqb` is the longest instruction name I know of. It shouldn't get any wider than this. * ARMeilleure: Remove SSE2+SHA requirement for GFNI * ARMeilleure Add `X86GetGf2p8LogicalShiftLeft` Used to generate GF(2^8) 8x8 bit-matrices for bit-shifting for the `gf2p8affineqb` instruction. * ARMeilleure: Append `FeatureInfo7Ecx` to `FeatureInfo`
This commit is contained in:
parent
96bf7f8522
commit
45ce540b9b
10 changed files with 589 additions and 409 deletions
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@ -113,6 +113,7 @@ namespace ARMeilleure.CodeGen.X86
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Add(X86Instruction.Divps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5e, InstructionFlags.Vex));
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Add(X86Instruction.Divps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5e, InstructionFlags.Vex));
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Add(X86Instruction.Divsd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5e, InstructionFlags.Vex | InstructionFlags.PrefixF2));
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Add(X86Instruction.Divsd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5e, InstructionFlags.Vex | InstructionFlags.PrefixF2));
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Add(X86Instruction.Divss, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5e, InstructionFlags.Vex | InstructionFlags.PrefixF3));
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Add(X86Instruction.Divss, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5e, InstructionFlags.Vex | InstructionFlags.PrefixF3));
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Add(X86Instruction.Gf2p8affineqb, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f3ace, InstructionFlags.Prefix66));
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Add(X86Instruction.Haddpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f7c, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Haddpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f7c, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Haddps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f7c, InstructionFlags.Vex | InstructionFlags.PrefixF2));
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Add(X86Instruction.Haddps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f7c, InstructionFlags.Vex | InstructionFlags.PrefixF2));
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Add(X86Instruction.Idiv, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x070000f7, InstructionFlags.None));
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Add(X86Instruction.Idiv, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x070000f7, InstructionFlags.None));
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@ -20,8 +20,9 @@ namespace ARMeilleure.CodeGen.X86
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if (maxNum >= 7)
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if (maxNum >= 7)
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{
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{
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(_, int ebx7, _, _) = X86Base.CpuId(0x00000007, 0x00000000);
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(_, int ebx7, int ecx7, _) = X86Base.CpuId(0x00000007, 0x00000000);
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FeatureInfo7Ebx = (FeatureFlags7Ebx)ebx7;
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FeatureInfo7Ebx = (FeatureFlags7Ebx)ebx7;
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FeatureInfo7Ecx = (FeatureFlags7Ecx)ecx7;
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}
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}
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}
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}
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@ -54,9 +55,16 @@ namespace ARMeilleure.CodeGen.X86
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Sha = 1 << 29
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Sha = 1 << 29
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}
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}
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[Flags]
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public enum FeatureFlags7Ecx
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{
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Gfni = 1 << 8,
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}
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public static FeatureFlags1Edx FeatureInfo1Edx { get; }
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public static FeatureFlags1Edx FeatureInfo1Edx { get; }
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public static FeatureFlags1Ecx FeatureInfo1Ecx { get; }
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public static FeatureFlags1Ecx FeatureInfo1Ecx { get; }
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public static FeatureFlags7Ebx FeatureInfo7Ebx { get; } = 0;
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public static FeatureFlags7Ebx FeatureInfo7Ebx { get; } = 0;
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public static FeatureFlags7Ecx FeatureInfo7Ecx { get; } = 0;
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public static bool SupportsSse => FeatureInfo1Edx.HasFlag(FeatureFlags1Edx.Sse);
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public static bool SupportsSse => FeatureInfo1Edx.HasFlag(FeatureFlags1Edx.Sse);
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public static bool SupportsSse2 => FeatureInfo1Edx.HasFlag(FeatureFlags1Edx.Sse2);
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public static bool SupportsSse2 => FeatureInfo1Edx.HasFlag(FeatureFlags1Edx.Sse2);
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@ -72,6 +80,7 @@ namespace ARMeilleure.CodeGen.X86
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public static bool SupportsAvx2 => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx2) && SupportsAvx;
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public static bool SupportsAvx2 => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx2) && SupportsAvx;
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public static bool SupportsF16c => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.F16c);
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public static bool SupportsF16c => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.F16c);
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public static bool SupportsSha => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Sha);
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public static bool SupportsSha => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Sha);
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public static bool SupportsGfni => FeatureInfo7Ecx.HasFlag(FeatureFlags7Ecx.Gfni);
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public static bool ForceLegacySse { get; set; }
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public static bool ForceLegacySse { get; set; }
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@ -58,6 +58,7 @@ namespace ARMeilleure.CodeGen.X86
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Add(Intrinsic.X86Divps, new IntrinsicInfo(X86Instruction.Divps, IntrinsicType.Binary));
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Add(Intrinsic.X86Divps, new IntrinsicInfo(X86Instruction.Divps, IntrinsicType.Binary));
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Add(Intrinsic.X86Divsd, new IntrinsicInfo(X86Instruction.Divsd, IntrinsicType.Binary));
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Add(Intrinsic.X86Divsd, new IntrinsicInfo(X86Instruction.Divsd, IntrinsicType.Binary));
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Add(Intrinsic.X86Divss, new IntrinsicInfo(X86Instruction.Divss, IntrinsicType.Binary));
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Add(Intrinsic.X86Divss, new IntrinsicInfo(X86Instruction.Divss, IntrinsicType.Binary));
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Add(Intrinsic.X86Gf2p8affineqb, new IntrinsicInfo(X86Instruction.Gf2p8affineqb, IntrinsicType.TernaryImm));
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Add(Intrinsic.X86Haddpd, new IntrinsicInfo(X86Instruction.Haddpd, IntrinsicType.Binary));
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Add(Intrinsic.X86Haddpd, new IntrinsicInfo(X86Instruction.Haddpd, IntrinsicType.Binary));
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Add(Intrinsic.X86Haddps, new IntrinsicInfo(X86Instruction.Haddps, IntrinsicType.Binary));
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Add(Intrinsic.X86Haddps, new IntrinsicInfo(X86Instruction.Haddps, IntrinsicType.Binary));
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Add(Intrinsic.X86Insertps, new IntrinsicInfo(X86Instruction.Insertps, IntrinsicType.TernaryImm));
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Add(Intrinsic.X86Insertps, new IntrinsicInfo(X86Instruction.Insertps, IntrinsicType.TernaryImm));
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@ -54,6 +54,7 @@ namespace ARMeilleure.CodeGen.X86
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Divps,
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Divps,
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Divsd,
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Divsd,
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Divss,
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Divss,
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Gf2p8affineqb,
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Haddpd,
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Haddpd,
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Haddps,
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Haddps,
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Idiv,
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Idiv,
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@ -243,6 +243,21 @@ namespace ARMeilleure.Instructions
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throw new ArgumentException($"Invalid rounding mode \"{roundMode}\".");
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throw new ArgumentException($"Invalid rounding mode \"{roundMode}\".");
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}
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}
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public static ulong X86GetGf2p8LogicalShiftLeft(int shift)
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{
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ulong identity =
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(0b00000001UL << 56) |
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(0b00000010UL << 48) |
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(0b00000100UL << 40) |
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(0b00001000UL << 32) |
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(0b00010000UL << 24) |
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(0b00100000UL << 16) |
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(0b01000000UL << 8) |
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(0b10000000UL << 0);
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return shift >= 0 ? identity >> (shift * 8) : identity << (-shift * 8);
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}
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public static Operand EmitCountSetBits8(ArmEmitterContext context, Operand op) // "size" is 8 (SIMD&FP Inst.).
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public static Operand EmitCountSetBits8(ArmEmitterContext context, Operand op) // "size" is 8 (SIMD&FP Inst.).
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{
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{
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Debug.Assert(op.Type == OperandType.I32 || op.Type == OperandType.I64);
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Debug.Assert(op.Type == OperandType.I32 || op.Type == OperandType.I64);
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@ -336,8 +336,32 @@ namespace ARMeilleure.Instructions
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{
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand res = context.VectorZero();
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if (Optimizations.UseGfni)
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{
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const long bitMatrix =
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(0b10000000L << 56) |
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(0b01000000L << 48) |
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(0b00100000L << 40) |
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(0b00010000L << 32) |
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(0b00001000L << 24) |
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(0b00000100L << 16) |
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(0b00000010L << 8) |
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(0b00000001L << 0);
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Operand vBitMatrix = X86GetAllElements(context, bitMatrix);
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Operand res = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, GetVec(op.Rn), vBitMatrix, Const(0));
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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Operand res = context.VectorZero();
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int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8;
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int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8;
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for (int index = 0; index < elems; index++)
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for (int index = 0; index < elems; index++)
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context.Copy(GetVec(op.Rd), res);
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context.Copy(GetVec(op.Rd), res);
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}
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}
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}
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private static Operand EmitReverseBits8Op(ArmEmitterContext context, Operand op)
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private static Operand EmitReverseBits8Op(ArmEmitterContext context, Operand op)
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{
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{
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@ -88,8 +88,35 @@ namespace ARMeilleure.Instructions
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OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
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OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
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int shift = GetImmShl(op);
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int shift = GetImmShl(op);
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int eSize = 8 << op.Size;
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if (Optimizations.UseSse2 && op.Size > 0)
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if (shift >= eSize)
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{
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if ((op.RegisterSize == RegisterSize.Simd64))
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{
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Operand res = context.VectorZeroUpper64(GetVec(op.Rd));
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context.Copy(GetVec(op.Rd), res);
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}
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}
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else if (Optimizations.UseGfni && op.Size == 0)
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{
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Operand n = GetVec(op.Rn);
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ulong bitMatrix = X86GetGf2p8LogicalShiftLeft(shift);
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Operand vBitMatrix = X86GetElements(context, bitMatrix, bitMatrix);
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Operand res = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, n, vBitMatrix, Const(0));
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else if (Optimizations.UseSse2 && op.Size > 0)
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{
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{
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Operand n = GetVec(op.Rn);
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Operand n = GetVec(op.Rn);
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{
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{
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OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
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OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
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if (Optimizations.UseSse2 && op.Size > 0 && op.Size < 3)
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{
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int shift = GetImmShr(op);
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int shift = GetImmShr(op);
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if (Optimizations.UseGfni && op.Size == 0)
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{
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Operand n = GetVec(op.Rn);
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ulong bitMatrix;
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if (shift < 8)
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{
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bitMatrix = X86GetGf2p8LogicalShiftLeft(-shift);
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// Extend sign-bit
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bitMatrix |= 0x8080808080808080UL >> (64 - shift * 8);
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}
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else
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{
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// Replicate sign-bit into all bits
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bitMatrix = 0x8080808080808080UL;
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}
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Operand vBitMatrix = X86GetElements(context, bitMatrix, bitMatrix);
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Operand res = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, n, vBitMatrix, Const(0));
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else if (Optimizations.UseSse2 && op.Size > 0 && op.Size < 3)
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{
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Operand n = GetVec(op.Rn);
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Operand n = GetVec(op.Rn);
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Intrinsic sraInst = X86PsraInstruction[op.Size];
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Intrinsic sraInst = X86PsraInstruction[op.Size];
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OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
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OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
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int shift = GetImmShl(op);
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int shift = GetImmShl(op);
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int eSize = 8 << op.Size;
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ulong mask = shift != 0 ? ulong.MaxValue >> (64 - shift) : 0UL;
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ulong mask = shift != 0 ? ulong.MaxValue >> (64 - shift) : 0UL;
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if (Optimizations.UseSse2 && op.Size > 0)
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if (shift >= eSize)
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{
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if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
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{
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Operand res = context.VectorZeroUpper64(GetVec(op.Rd));
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context.Copy(GetVec(op.Rd), res);
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}
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}
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else if (Optimizations.UseGfni && op.Size == 0)
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{
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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ulong bitMatrix = X86GetGf2p8LogicalShiftLeft(shift);
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Operand vBitMatrix = X86GetElements(context, bitMatrix, bitMatrix);
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Operand nShifted = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, n, vBitMatrix, Const(0));
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Operand dMask = X86GetAllElements(context, (long)mask * _masks_SliSri[op.Size]);
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Operand dMasked = context.AddIntrinsic(Intrinsic.X86Pand, d, dMask);
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Operand res = context.AddIntrinsic(Intrinsic.X86Por, nShifted, dMasked);
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if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(d, res);
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}
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else if (Optimizations.UseSse2 && op.Size > 0)
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{
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{
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Operand d = GetVec(op.Rd);
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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Operand n = GetVec(op.Rn);
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ulong mask = (ulong.MaxValue << (eSize - shift)) & (ulong.MaxValue >> (64 - eSize));
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ulong mask = (ulong.MaxValue << (eSize - shift)) & (ulong.MaxValue >> (64 - eSize));
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if (Optimizations.UseSse2 && op.Size > 0)
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if (shift >= eSize)
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{
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if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
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{
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Operand res = context.VectorZeroUpper64(GetVec(op.Rd));
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context.Copy(GetVec(op.Rd), res);
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}
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}
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else if (Optimizations.UseGfni && op.Size == 0)
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{
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Operand d = GetVec(op.Rd);
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Operand n = GetVec(op.Rn);
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ulong bitMatrix = X86GetGf2p8LogicalShiftLeft(-shift);
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Operand vBitMatrix = X86GetElements(context, bitMatrix, bitMatrix);
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Operand nShifted = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, n, vBitMatrix, Const(0));
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||||||
|
Operand dMask = X86GetAllElements(context, (long)mask * _masks_SliSri[op.Size]);
|
||||||
|
|
||||||
|
Operand dMasked = context.AddIntrinsic(Intrinsic.X86Pand, d, dMask);
|
||||||
|
|
||||||
|
Operand res = context.AddIntrinsic(Intrinsic.X86Por, nShifted, dMasked);
|
||||||
|
|
||||||
|
if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
|
||||||
|
{
|
||||||
|
res = context.VectorZeroUpper64(res);
|
||||||
|
}
|
||||||
|
|
||||||
|
context.Copy(d, res);
|
||||||
|
}
|
||||||
|
else if (Optimizations.UseSse2 && op.Size > 0)
|
||||||
{
|
{
|
||||||
Operand d = GetVec(op.Rd);
|
Operand d = GetVec(op.Rd);
|
||||||
Operand n = GetVec(op.Rn);
|
Operand n = GetVec(op.Rn);
|
||||||
|
|
|
@ -47,6 +47,7 @@ namespace ARMeilleure.IntermediateRepresentation
|
||||||
X86Divps,
|
X86Divps,
|
||||||
X86Divsd,
|
X86Divsd,
|
||||||
X86Divss,
|
X86Divss,
|
||||||
|
X86Gf2p8affineqb,
|
||||||
X86Haddpd,
|
X86Haddpd,
|
||||||
X86Haddps,
|
X86Haddps,
|
||||||
X86Insertps,
|
X86Insertps,
|
||||||
|
|
|
@ -22,6 +22,7 @@ namespace ARMeilleure
|
||||||
public static bool UseAesniIfAvailable { get; set; } = true;
|
public static bool UseAesniIfAvailable { get; set; } = true;
|
||||||
public static bool UsePclmulqdqIfAvailable { get; set; } = true;
|
public static bool UsePclmulqdqIfAvailable { get; set; } = true;
|
||||||
public static bool UseShaIfAvailable { get; set; } = true;
|
public static bool UseShaIfAvailable { get; set; } = true;
|
||||||
|
public static bool UseGfniIfAvailable { get; set; } = true;
|
||||||
|
|
||||||
public static bool ForceLegacySse
|
public static bool ForceLegacySse
|
||||||
{
|
{
|
||||||
|
@ -42,5 +43,6 @@ namespace ARMeilleure
|
||||||
internal static bool UseAesni => UseAesniIfAvailable && HardwareCapabilities.SupportsAesni;
|
internal static bool UseAesni => UseAesniIfAvailable && HardwareCapabilities.SupportsAesni;
|
||||||
internal static bool UsePclmulqdq => UsePclmulqdqIfAvailable && HardwareCapabilities.SupportsPclmulqdq;
|
internal static bool UsePclmulqdq => UsePclmulqdqIfAvailable && HardwareCapabilities.SupportsPclmulqdq;
|
||||||
internal static bool UseSha => UseShaIfAvailable && HardwareCapabilities.SupportsSha;
|
internal static bool UseSha => UseShaIfAvailable && HardwareCapabilities.SupportsSha;
|
||||||
|
internal static bool UseGfni => UseGfniIfAvailable && HardwareCapabilities.SupportsGfni;
|
||||||
}
|
}
|
||||||
}
|
}
|
|
@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
|
||||||
private const string OuterHeaderMagicString = "PTCohd\0\0";
|
private const string OuterHeaderMagicString = "PTCohd\0\0";
|
||||||
private const string InnerHeaderMagicString = "PTCihd\0\0";
|
private const string InnerHeaderMagicString = "PTCihd\0\0";
|
||||||
|
|
||||||
private const uint InternalVersion = 3703; //! To be incremented manually for each change to the ARMeilleure project.
|
private const uint InternalVersion = 3710; //! To be incremented manually for each change to the ARMeilleure project.
|
||||||
|
|
||||||
private const string ActualDir = "0";
|
private const string ActualDir = "0";
|
||||||
private const string BackupDir = "1";
|
private const string BackupDir = "1";
|
||||||
|
@ -951,7 +951,8 @@ namespace ARMeilleure.Translation.PTC
|
||||||
return new FeatureInfo(
|
return new FeatureInfo(
|
||||||
(uint)HardwareCapabilities.FeatureInfo1Ecx,
|
(uint)HardwareCapabilities.FeatureInfo1Ecx,
|
||||||
(uint)HardwareCapabilities.FeatureInfo1Edx,
|
(uint)HardwareCapabilities.FeatureInfo1Edx,
|
||||||
(uint)HardwareCapabilities.FeatureInfo7Ebx);
|
(uint)HardwareCapabilities.FeatureInfo7Ebx,
|
||||||
|
(uint)HardwareCapabilities.FeatureInfo7Ecx);
|
||||||
}
|
}
|
||||||
|
|
||||||
private static byte GetMemoryManagerMode()
|
private static byte GetMemoryManagerMode()
|
||||||
|
@ -971,7 +972,7 @@ namespace ARMeilleure.Translation.PTC
|
||||||
return osPlatform;
|
return osPlatform;
|
||||||
}
|
}
|
||||||
|
|
||||||
[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 54*/)]
|
[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 58*/)]
|
||||||
private struct OuterHeader
|
private struct OuterHeader
|
||||||
{
|
{
|
||||||
public ulong Magic;
|
public ulong Magic;
|
||||||
|
@ -1002,8 +1003,8 @@ namespace ARMeilleure.Translation.PTC
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 12*/)]
|
[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 16*/)]
|
||||||
private record struct FeatureInfo(uint FeatureInfo0, uint FeatureInfo1, uint FeatureInfo2);
|
private record struct FeatureInfo(uint FeatureInfo0, uint FeatureInfo1, uint FeatureInfo2, uint FeatureInfo3);
|
||||||
|
|
||||||
[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 128*/)]
|
[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 128*/)]
|
||||||
private struct InnerHeader
|
private struct InnerHeader
|
||||||
|
|
Loading…
Reference in a new issue