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https://github.com/Ryujinx/Ryujinx.git
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Implement VRINT (vector) Arm32 NEON instructions (#3691)
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parent
1529e6cf0d
commit
4d69286a9c
4 changed files with 144 additions and 2 deletions
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@ -959,6 +959,10 @@ namespace ARMeilleure.Decoders
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SetA32("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps, InstEmit32.Vrecps, OpCode32SimdReg.Create);
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SetA32("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps, InstEmit32.Vrecps, OpCode32SimdReg.Create);
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SetA32("111100111x11xx00xxxx000<<xx0xxxx", InstName.Vrev, InstEmit32.Vrev, OpCode32SimdRev.Create);
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SetA32("111100111x11xx00xxxx000<<xx0xxxx", InstName.Vrev, InstEmit32.Vrev, OpCode32SimdRev.Create);
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SetA32("1111001x0x<<xxxxxxxx0001xxx0xxxx", InstName.Vrhadd, InstEmit32.Vrhadd, OpCode32SimdReg.Create);
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SetA32("1111001x0x<<xxxxxxxx0001xxx0xxxx", InstName.Vrhadd, InstEmit32.Vrhadd, OpCode32SimdReg.Create);
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SetA32("111100111x111010xxxx01010xx0xxxx", InstName.Vrinta, InstEmit32.Vrinta_V, OpCode32SimdCmpZ.Create);
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SetA32("111100111x111010xxxx01101xx0xxxx", InstName.Vrintm, InstEmit32.Vrintm_V, OpCode32SimdCmpZ.Create);
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SetA32("111100111x111010xxxx01000xx0xxxx", InstName.Vrintn, InstEmit32.Vrintn_V, OpCode32SimdCmpZ.Create);
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SetA32("111100111x111010xxxx01111xx0xxxx", InstName.Vrintp, InstEmit32.Vrintp_V, OpCode32SimdCmpZ.Create);
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SetA32("1111001x1x>>>xxxxxxx0010>xx1xxxx", InstName.Vrshr, InstEmit32.Vrshr, OpCode32SimdShImm.Create);
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SetA32("1111001x1x>>>xxxxxxx0010>xx1xxxx", InstName.Vrshr, InstEmit32.Vrshr, OpCode32SimdShImm.Create);
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SetA32("111100101x>>>xxxxxxx100001x1xxx0", InstName.Vrshrn, InstEmit32.Vrshrn, OpCode32SimdShImmNarrow.Create);
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SetA32("111100101x>>>xxxxxxx100001x1xxx0", InstName.Vrshrn, InstEmit32.Vrshrn, OpCode32SimdShImmNarrow.Create);
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SetA32("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte, InstEmit32.Vrsqrte, OpCode32SimdSqrte.Create);
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SetA32("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte, InstEmit32.Vrsqrte, OpCode32SimdSqrte.Create);
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@ -323,6 +323,60 @@ namespace ARMeilleure.Instructions
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}
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}
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}
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}
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// VRINTA (vector).
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public static void Vrinta_V(ArmEmitterContext context)
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{
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EmitVectorUnaryOpF32(context, (m) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, m));
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}
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// VRINTM (vector).
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public static void Vrintm_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorUnaryOpSimd32(context, (m) =>
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{
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return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.TowardsMinusInfinity)));
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});
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}
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else
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{
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EmitVectorUnaryOpF32(context, (m) => EmitUnaryMathCall(context, nameof(Math.Floor), m));
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}
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}
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// VRINTN (vector).
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public static void Vrintn_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorUnaryOpSimd32(context, (m) =>
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{
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return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
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});
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}
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else
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{
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EmitVectorUnaryOpF32(context, (m) => EmitRoundMathCall(context, MidpointRounding.ToEven, m));
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}
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}
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// VRINTP (vector).
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public static void Vrintp_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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EmitVectorUnaryOpSimd32(context, (m) =>
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{
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return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.TowardsPlusInfinity)));
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});
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}
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else
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{
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EmitVectorUnaryOpF32(context, (m) => EmitUnaryMathCall(context, nameof(Math.Ceiling), m));
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}
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}
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// VRINTZ (floating-point).
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// VRINTZ (floating-point).
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public static void Vrint_Z(ArmEmitterContext context)
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public static void Vrint_Z(ArmEmitterContext context)
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{
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{
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@ -636,6 +636,10 @@ namespace ARMeilleure.Instructions
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Vrev,
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Vrev,
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Vrhadd,
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Vrhadd,
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Vrint,
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Vrint,
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Vrinta,
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Vrintm,
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Vrintn,
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Vrintp,
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Vrintx,
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Vrintx,
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Vrshr,
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Vrshr,
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Vrshrn,
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Vrshrn,
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@ -13,6 +13,16 @@ namespace Ryujinx.Tests.Cpu
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#if SimdCvt32
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#if SimdCvt32
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#region "ValueSource (Opcodes)"
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#region "ValueSource (Opcodes)"
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private static uint[] _Vrint_AMNP_V_F32_()
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{
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return new uint[]
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{
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0xf3ba0500u, // VRINTA.F32 Q0, Q0
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0xf3ba0680u, // VRINTM.F32 Q0, Q0
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0xf3ba0400u, // VRINTN.F32 Q0, Q0
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0xf3ba0780u // VRINTP.F32 Q0, Q0
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};
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}
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#endregion
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#endregion
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#region "ValueSource (Types)"
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#region "ValueSource (Types)"
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@ -64,6 +74,47 @@ namespace Ryujinx.Tests.Cpu
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}
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}
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}
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}
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private static IEnumerable<ulong> _2S_F_()
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{
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yield return 0xFF7FFFFFFF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0x8080000080800000ul; // -Min Normal
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yield return 0x807FFFFF807FFFFFul; // -Max Subnormal
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yield return 0x8000000180000001ul; // -Min Subnormal (-float.Epsilon)
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yield return 0x7F7FFFFF7F7FFFFFul; // +Max Normal (float.MaxValue)
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yield return 0x0080000000800000ul; // +Min Normal
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yield return 0x007FFFFF007FFFFFul; // +Max Subnormal
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yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon)
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if (!NoZeros)
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{
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yield return 0x8000000080000000ul; // -Zero
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yield return 0x0000000000000000ul; // +Zero
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}
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if (!NoInfs)
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{
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yield return 0xFF800000FF800000ul; // -Infinity
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yield return 0x7F8000007F800000ul; // +Infinity
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}
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if (!NoNaNs)
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{
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yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
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yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x7FC000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
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yield return 0x7FBFFFFF7FBFFFFFul; // +SNaN (all ones payload)
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}
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for (int cnt = 1; cnt <= RndCnt; cnt++)
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{
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ulong rnd1 = GenNormalS();
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ulong rnd2 = GenSubnormalS();
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yield return (rnd1 << 32) | rnd1;
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yield return (rnd2 << 32) | rnd2;
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}
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}
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private static IEnumerable<ulong> _1D_F_()
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private static IEnumerable<ulong> _1D_F_()
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{
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{
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yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal (double.MinValue)
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yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal (double.MinValue)
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@ -224,6 +275,35 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Test, Pairwise] [Explicit]
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public void Vrint_AMNP_V_F32([ValueSource(nameof(_Vrint_AMNP_V_F32_))] uint opcode,
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[Values(0u, 1u, 2u, 3u)] uint rd,
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[Values(0u, 1u, 2u, 3u)] uint rm,
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[ValueSource(nameof(_2S_F_))] ulong d0,
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[ValueSource(nameof(_2S_F_))] ulong d1,
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[ValueSource(nameof(_2S_F_))] ulong d2,
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[ValueSource(nameof(_2S_F_))] ulong d3,
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[Values] bool q)
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{
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if (q)
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{
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opcode |= 1 << 6;
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rd >>= 1; rd <<= 1;
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rm >>= 1; rm <<= 1;
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}
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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V128 v0 = MakeVectorE0E1(d0, d1);
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V128 v1 = MakeVectorE0E1(d2, d3);
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SingleOpcode(opcode, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VRINTX.F<size> <Sd>, <Sm>")]
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[Test, Pairwise, Description("VRINTX.F<size> <Sd>, <Sm>")]
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public void Vrintx_S([Values(0u, 1u)] uint rd,
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public void Vrintx_S([Values(0u, 1u)] uint rd,
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[Values(0u, 1u)] uint rm,
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[Values(0u, 1u)] uint rm,
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