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Add Smaxv_V, Sminv_V, Umaxv_V, Uminv_V Inst.; add Tests. (#691)
* Update InstEmitSimdHelper.cs * Update InstEmitSimdArithmetic.cs * Update OpCodeTable.cs * Update CpuTestSimd.cs
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12badfffb9
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51ea6fa583
4 changed files with 118 additions and 35 deletions
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@ -68,21 +68,7 @@ namespace ChocolArm64.Instructions
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public static void Addv_V(ILEmitterCtx context)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int bytes = op.GetBitsCount() >> 3;
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int elems = bytes >> op.Size;
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EmitVectorExtractZx(context, op.Rn, 0, op.Size);
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for (int index = 1; index < elems; index++)
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{
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EmitVectorExtractZx(context, op.Rn, index, op.Size);
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context.Emit(OpCodes.Add);
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}
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EmitScalarSet(context, op.Rd, op.Size);
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EmitVectorAcrossVectorOpZx(context, () => context.Emit(OpCodes.Add));
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}
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public static void Cls_V(ILEmitterCtx context)
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@ -2388,6 +2374,15 @@ namespace ChocolArm64.Instructions
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EmitVectorPairwiseOpSx(context, () => context.EmitCall(mthdInfo));
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}
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public static void Smaxv_V(ILEmitterCtx context)
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{
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Type[] types = new Type[] { typeof(long), typeof(long) };
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MethodInfo mthdInfo = typeof(Math).GetMethod(nameof(Math.Max), types);
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EmitVectorAcrossVectorOpSx(context, () => context.EmitCall(mthdInfo));
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}
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public static void Smin_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse41)
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@ -2429,6 +2424,15 @@ namespace ChocolArm64.Instructions
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EmitVectorPairwiseOpSx(context, () => context.EmitCall(mthdInfo));
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}
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public static void Sminv_V(ILEmitterCtx context)
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{
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Type[] types = new Type[] { typeof(long), typeof(long) };
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MethodInfo mthdInfo = typeof(Math).GetMethod(nameof(Math.Min), types);
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EmitVectorAcrossVectorOpSx(context, () => context.EmitCall(mthdInfo));
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}
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public static void Smlal_V(ILEmitterCtx context)
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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@ -3208,6 +3212,15 @@ namespace ChocolArm64.Instructions
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EmitVectorPairwiseOpZx(context, () => context.EmitCall(mthdInfo));
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}
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public static void Umaxv_V(ILEmitterCtx context)
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{
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Type[] types = new Type[] { typeof(ulong), typeof(ulong) };
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MethodInfo mthdInfo = typeof(Math).GetMethod(nameof(Math.Max), types);
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EmitVectorAcrossVectorOpZx(context, () => context.EmitCall(mthdInfo));
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}
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public static void Umin_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse41)
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@ -3249,6 +3262,15 @@ namespace ChocolArm64.Instructions
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EmitVectorPairwiseOpZx(context, () => context.EmitCall(mthdInfo));
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}
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public static void Uminv_V(ILEmitterCtx context)
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{
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Type[] types = new Type[] { typeof(ulong), typeof(ulong) };
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MethodInfo mthdInfo = typeof(Math).GetMethod(nameof(Math.Min), types);
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EmitVectorAcrossVectorOpZx(context, () => context.EmitCall(mthdInfo));
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}
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public static void Umlal_V(ILEmitterCtx context)
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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@ -821,6 +821,35 @@ namespace ChocolArm64.Instructions
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}
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}
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public static void EmitVectorAcrossVectorOpSx(ILEmitterCtx context, Action emit)
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{
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EmitVectorAcrossVectorOp(context, emit, true);
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}
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public static void EmitVectorAcrossVectorOpZx(ILEmitterCtx context, Action emit)
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{
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EmitVectorAcrossVectorOp(context, emit, false);
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}
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public static void EmitVectorAcrossVectorOp(ILEmitterCtx context, Action emit, bool signed)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int bytes = op.GetBitsCount() >> 3;
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int elems = bytes >> op.Size;
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EmitVectorExtract(context, op.Rn, 0, op.Size, signed);
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for (int index = 1; index < elems; index++)
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{
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EmitVectorExtract(context, op.Rn, index, op.Size, signed);
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emit();
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}
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EmitScalarSet(context, op.Rd, op.Size);
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}
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public static void EmitVectorPairwiseOpF(ILEmitterCtx context, Action emit)
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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@ -461,8 +461,12 @@ namespace ChocolArm64
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SetA64("0x1011110>>>>xxx010101xxxxxxxxxx", InstEmit.Sli_V, typeof(OpCodeSimdShImm64));
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SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", InstEmit.Smax_V, typeof(OpCodeSimdReg64));
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SetA64("0x001110<<1xxxxx101001xxxxxxxxxx", InstEmit.Smaxp_V, typeof(OpCodeSimdReg64));
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SetA64("000011100x110000101010xxxxxxxxxx", InstEmit.Smaxv_V, typeof(OpCodeSimd64));
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SetA64("01001110<<110000101010xxxxxxxxxx", InstEmit.Smaxv_V, typeof(OpCodeSimd64));
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SetA64("0x001110<<1xxxxx011011xxxxxxxxxx", InstEmit.Smin_V, typeof(OpCodeSimdReg64));
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SetA64("0x001110<<1xxxxx101011xxxxxxxxxx", InstEmit.Sminp_V, typeof(OpCodeSimdReg64));
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SetA64("000011100x110001101010xxxxxxxxxx", InstEmit.Sminv_V, typeof(OpCodeSimd64));
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SetA64("01001110<<110001101010xxxxxxxxxx", InstEmit.Sminv_V, typeof(OpCodeSimd64));
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SetA64("0x001110<<1xxxxx100000xxxxxxxxxx", InstEmit.Smlal_V, typeof(OpCodeSimdReg64));
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SetA64("0x001111xxxxxxxx0010x0xxxxxxxxxx", InstEmit.Smlal_Ve, typeof(OpCodeSimdRegElem64));
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SetA64("0x001110<<1xxxxx101000xxxxxxxxxx", InstEmit.Smlsl_V, typeof(OpCodeSimdReg64));
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@ -556,8 +560,12 @@ namespace ChocolArm64
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SetA64("0x101110<<1xxxxx001001xxxxxxxxxx", InstEmit.Uhsub_V, typeof(OpCodeSimdReg64));
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SetA64("0x101110<<1xxxxx011001xxxxxxxxxx", InstEmit.Umax_V, typeof(OpCodeSimdReg64));
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SetA64("0x101110<<1xxxxx101001xxxxxxxxxx", InstEmit.Umaxp_V, typeof(OpCodeSimdReg64));
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SetA64("001011100x110000101010xxxxxxxxxx", InstEmit.Umaxv_V, typeof(OpCodeSimd64));
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SetA64("01101110<<110000101010xxxxxxxxxx", InstEmit.Umaxv_V, typeof(OpCodeSimd64));
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SetA64("0x101110<<1xxxxx011011xxxxxxxxxx", InstEmit.Umin_V, typeof(OpCodeSimdReg64));
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SetA64("0x101110<<1xxxxx101011xxxxxxxxxx", InstEmit.Uminp_V, typeof(OpCodeSimdReg64));
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SetA64("001011100x110001101010xxxxxxxxxx", InstEmit.Uminv_V, typeof(OpCodeSimd64));
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SetA64("01101110<<110001101010xxxxxxxxxx", InstEmit.Uminv_V, typeof(OpCodeSimd64));
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SetA64("0x101110<<1xxxxx100000xxxxxxxxxx", InstEmit.Umlal_V, typeof(OpCodeSimdReg64));
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SetA64("0x101111xxxxxxxx0010x0xxxxxxxxxx", InstEmit.Umlal_Ve, typeof(OpCodeSimdRegElem64));
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SetA64("0x101110<<1xxxxx101000xxxxxxxxxx", InstEmit.Umlsl_V, typeof(OpCodeSimdReg64));
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@ -445,6 +445,30 @@ namespace Ryujinx.Tests.Cpu
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _SU_Add_Max_Min_V_V_8BB_4HH_()
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{
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return new uint[]
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{
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0x0E31B800u, // ADDV B0, V0.8B
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0x0E30A800u, // SMAXV B0, V0.8B
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0x0E31A800u, // SMINV B0, V0.8B
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0x2E30A800u, // UMAXV B0, V0.8B
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0x2E31A800u // UMINV B0, V0.8B
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};
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}
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private static uint[] _SU_Add_Max_Min_V_V_16BB_8HH_4SS_()
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{
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return new uint[]
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{
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0x4E31B800u, // ADDV B0, V0.16B
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0x4E30A800u, // SMAXV B0, V0.16B
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0x4E31A800u, // SMINV B0, V0.16B
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0x6E30A800u, // UMAXV B0, V0.16B
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0x6E31A800u // UMINV B0, V0.16B
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};
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}
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private static uint[] _F_Abs_Neg_Recpx_Sqrt_S_S_()
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{
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return new uint[]
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@ -913,40 +937,40 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ADDV <V><d>, <Vn>.<T>")]
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public void Addv_V_8BB_4HH([Values(0u)] uint rd,
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[Test, Pairwise]
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public void SU_Add_Max_Min_V_V_8BB_4HH([ValueSource("_SU_Add_Max_Min_V_V_8BB_4HH_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_8B4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B4H_")] [Random(RndCnt)] ulong a,
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[Values(0b00u, 0b01u)] uint size) // <8BB, 4HH>
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{
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uint opcode = 0x0E31B800; // ADDV B0, V0.8B
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((size & 3) << 22);
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((size & 3) << 22);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0(a);
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SingleOpcode(opcode, v0: v0, v1: v1);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ADDV <V><d>, <Vn>.<T>")]
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public void Addv_V_16BB_8HH_4SS([Values(0u)] uint rd,
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[Test, Pairwise]
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public void SU_Add_Max_Min_V_V_16BB_8HH_4SS([ValueSource("_SU_Add_Max_Min_V_V_16BB_8HH_4SS_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong a,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16BB, 8HH, 4SS>
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{
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uint opcode = 0x4E31B800; // ADDV B0, V0.16B
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((size & 3) << 22);
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((size & 3) << 22);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(a, a);
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SingleOpcode(opcode, v0: v0, v1: v1);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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