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Add Fpscr.Qc = 1 if sat. for Vqrshrn & Vqrshrun.
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4 changed files with 19 additions and 9 deletions
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@ -289,7 +289,7 @@ namespace ARMeilleure.Instructions
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context.BranchIfFalse(lblNoSat, context.BitwiseOr(gt, lt));
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// TODO: Set QC (to 1) on FPSCR here.
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
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context.MarkLabel(lblNoSat);
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@ -145,6 +145,11 @@ namespace ARMeilleure.Instructions
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GetContext().Fpsr = (FPSR)value;
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}
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public static void SetFpsrQc()
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{
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GetContext().Fpsr |= FPSR.Qc;
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}
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public static void SetFpscr(uint fpscr)
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{
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var context = GetContext();
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@ -131,6 +131,7 @@ namespace ARMeilleure.Translation
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SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpcr)));
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SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpscr))); // A32 only.
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SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsr)));
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SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc))); // A32 only.
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SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl0)));
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SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl032))); // A32 only.
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SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SupervisorCall)));
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@ -173,7 +173,7 @@ namespace Ryujinx.Tests.Cpu
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public void Vshl_Imm([Values(0u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u, 3u)] uint size,
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[Random(RndCnt), Values(0u)] uint shiftImm,
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[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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@ -207,7 +207,7 @@ namespace Ryujinx.Tests.Cpu
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public void Vshrn_Imm([Values(0u, 1u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCnt), Values(0u)] uint shiftImm,
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[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b)
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@ -234,7 +234,7 @@ namespace Ryujinx.Tests.Cpu
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public void Vqrshrn_Imm([Values(0u, 1u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCnt), Values(0u)] uint shiftImm,
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[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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@ -258,16 +258,18 @@ namespace Ryujinx.Tests.Cpu
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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int fpscr = (int)TestContext.CurrentContext.Random.NextUInt() & (int)Fpsr.Qc;
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CompareAgainstUnicorn();
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr);
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CompareAgainstUnicorn(fpsrMask: Fpsr.Qc);
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}
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[Test, Pairwise, Description("VQRSHRUN.<type><size> <Vd>, <Vm>, #<imm>")]
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public void Vqrshrun_Imm([Values(0u, 1u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCnt), Values(0u)] uint shiftImm,
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[Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b)
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@ -285,9 +287,11 @@ namespace Ryujinx.Tests.Cpu
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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int fpscr = (int)TestContext.CurrentContext.Random.NextUInt() & (int)Fpsr.Qc;
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CompareAgainstUnicorn();
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr);
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CompareAgainstUnicorn(fpsrMask: Fpsr.Qc);
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}
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#endif
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}
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