From 74f52b34a1ea834fc1656895e39e656493a578de Mon Sep 17 00:00:00 2001 From: MS-DOS1999 Date: Fri, 20 Jul 2018 10:43:12 +0200 Subject: [PATCH] fix notNarrow VectorExtract, and add a tiny test to be sure that EmitSaturatingOp with notNarrow flag doesn't send errors --- ChocolArm64/Instruction/AInstEmitSimdHelper.cs | 8 +++++--- Ryujinx.Tests/Cpu/CpuTestSimd.cs | 13 +++++++++++++ Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs | 1 + 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs index 1b669547b9..8d1cccd876 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs @@ -884,7 +884,9 @@ namespace ChocolArm64.Instruction AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; - int Elems = !Scalar ? 8 >> Op.Size : 1; + int Bytes = Op.GetBitsCount() >> 3; + + int Elems = !Scalar ? (Narrow ? 8 : Bytes) >> Op.Size : 1; int ESize = 8 << Op.Size; @@ -912,11 +914,11 @@ namespace ChocolArm64.Instruction AILLabel LblLe = new AILLabel(); AILLabel LblGeEnd = new AILLabel(); - EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc); + EmitVectorExtract(Context, Op.Rn, Index, Narrow ? Op.Size + 1 : Op.Size, SignedSrc); if (Binary) { - EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Op.Size + 1, SignedSrc); + EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Narrow ? Op.Size + 1 : Op.Size, SignedSrc); } Emit(); diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs index 82591edaee..08aa0fd348 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs @@ -1126,6 +1126,19 @@ namespace Ryujinx.Tests.Cpu }); } + [TestCase(0x00000001u, 0x7FFFFFFFu, 0x7FFFFFFFu, true)] + public void Sqadd_S(uint A, uint B, uint Result, bool Fpsr) + { + Vector128 V1 = MakeVectorE0(A); + Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(0x5EA20C20, V1: V1, V2: V2); + Assert.Multiple(() => + { + Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + Assert.AreEqual(((ThreadState.Fpsr >> 27) & 1) == 1, Fpsr); + }); + } + [Test, Description("SQXTN , ")] public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs index 8e2d9a366e..b8d08fb3a7 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs @@ -9,6 +9,7 @@ namespace Ryujinx.Tests.Cpu { public class CpuTestSimdArithmetic : CpuTest { + [TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)] [TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000000000000ul)] [TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]