From 76a5972378b0c0980fa13fe23778a465b5e1900d Mon Sep 17 00:00:00 2001 From: MS-DOS1999 Date: Thu, 19 Apr 2018 05:22:12 +0200 Subject: [PATCH] Fix Fmin/max and add vector version, add and modifying fmin/max tests (#89) --- ChocolArm64/AOpCodeTable.cs | 2 + .../Instruction/AInstEmitSimdArithmetic.cs | 80 ++++++++++++++++++- ChocolArm64/Instruction/ASoftFallback.cs | 76 ++++++++++++++++++ Ryujinx.Tests/Cpu/CpuTestScalar.cs | 60 ++++++++++---- Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs | 52 ++++++++++++ 5 files changed, 250 insertions(+), 20 deletions(-) diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index d4cbd6fcb..fb74f8925 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -211,8 +211,10 @@ namespace ChocolArm64 Set("0>1011100<1xxxxx111111xxxxxxxxxx", AInstEmit.Fdiv_V, typeof(AOpCodeSimdReg)); Set("000111110x0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Fmadd_S, typeof(AOpCodeSimdReg)); Set("000111100x1xxxxx010010xxxxxxxxxx", AInstEmit.Fmax_S, typeof(AOpCodeSimdReg)); + Set("0x0011100x1xxxxx111101xxxxxxxxxx", AInstEmit.Fmax_V, typeof(AOpCodeSimdReg)); Set("000111100x1xxxxx011010xxxxxxxxxx", AInstEmit.Fmaxnm_S, typeof(AOpCodeSimdReg)); Set("000111100x1xxxxx010110xxxxxxxxxx", AInstEmit.Fmin_S, typeof(AOpCodeSimdReg)); + Set("0x0011101x1xxxxx111101xxxxxxxxxx", AInstEmit.Fmin_V, typeof(AOpCodeSimdReg)); Set("000111100x1xxxxx011110xxxxxxxxxx", AInstEmit.Fminnm_S, typeof(AOpCodeSimdReg)); Set("0>0011100<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmla_V, typeof(AOpCodeSimdReg)); Set("0x0011111< { - EmitBinaryMathCall(Context, nameof(Math.Max)); + if (Op.Size == 0) + { + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.MaxF)); + } + else if (Op.Size == 1) + { + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Max)); + } + else + { + throw new InvalidOperationException(); + } + }); + } + + public static void Fmax_V(AILEmitterCtx Context) + { + AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; + + EmitVectorBinaryOpF(Context, () => + { + if (Op.Size == 0) + { + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.MaxF)); + } + else if (Op.Size == 1) + { + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Max)); + } + else + { + throw new InvalidOperationException(); + } }); } public static void Fmin_S(AILEmitterCtx Context) { + AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; + EmitScalarBinaryOpF(Context, () => { - EmitBinaryMathCall(Context, nameof(Math.Min)); + if (Op.Size == 0) + { + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.MinF)); + } + else if (Op.Size == 1) + { + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Min)); + } + else + { + throw new InvalidOperationException(); + } + }); + } + + public static void Fmin_V(AILEmitterCtx Context) + { + AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; + + int SizeF = Op.Size & 1; + + EmitVectorBinaryOpF(Context, () => + { + if (SizeF == 0) + { + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.MinF)); + } + else if (SizeF == 1) + { + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Min)); + } + else + { + throw new InvalidOperationException(); + } }); } @@ -510,17 +580,19 @@ namespace ChocolArm64.Instruction { AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; + int SizeF = Op.Size & 1; + EmitVectorUnaryOpF(Context, () => { Context.EmitLdarg(ATranslatedSub.StateArgIdx); Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpcr)); - if (Op.Size == 2) + if (SizeF == 0) { ASoftFallback.EmitCall(Context, nameof(ASoftFallback.RoundF)); } - else if (Op.Size == 3) + else if (SizeF == 1) { ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Round)); } diff --git a/ChocolArm64/Instruction/ASoftFallback.cs b/ChocolArm64/Instruction/ASoftFallback.cs index 64f539fc8..c08f253e9 100644 --- a/ChocolArm64/Instruction/ASoftFallback.cs +++ b/ChocolArm64/Instruction/ASoftFallback.cs @@ -256,6 +256,82 @@ namespace ChocolArm64.Instruction ((Value >> 6) & 1) + (Value >> 7); } + public static float MaxF(float val1, float val2) + { + if (val1 == 0.0 && val2 == 0.0) + { + if (BitConverter.SingleToInt32Bits(val1) < 0 && BitConverter.SingleToInt32Bits(val2) < 0) + return -0.0f; + + return 0.0f; + } + + if (val1 > val2) + return val1; + + if (float.IsNaN(val1)) + return val1; + + return val2; + } + + public static double Max(double val1, double val2) + { + if (val1 == 0.0 && val2 == 0.0) + { + if (BitConverter.DoubleToInt64Bits(val1) < 0 && BitConverter.DoubleToInt64Bits(val2) < 0) + return -0.0; + + return 0.0; + } + + if (val1 > val2) + return val1; + + if (double.IsNaN(val1)) + return val1; + + return val2; + } + + public static float MinF(float val1, float val2) + { + if (val1 == 0.0 && val2 == 0.0) + { + if (BitConverter.SingleToInt32Bits(val1) < 0 || BitConverter.SingleToInt32Bits(val2) < 0) + return -0.0f; + + return 0.0f; + } + + if (val1 < val2) + return val1; + + if (float.IsNaN(val1)) + return val1; + + return val2; + } + + public static double Min(double val1, double val2) + { + if (val1 == 0.0 && val2 == 0.0) + { + if (BitConverter.DoubleToInt64Bits(val1) < 0 || BitConverter.DoubleToInt64Bits(val2) < 0) + return -0.0; + + return 0.0; + } + + if (val1 < val2) + return val1; + + if (double.IsNaN(val1)) + return val1; + + return val2; + } + public static float RoundF(float Value, int Fpcr) { switch ((ARoundMode)((Fpcr >> 22) & 3)) diff --git a/Ryujinx.Tests/Cpu/CpuTestScalar.cs b/Ryujinx.Tests/Cpu/CpuTestScalar.cs index ffe01a299..c7c3aa051 100644 --- a/Ryujinx.Tests/Cpu/CpuTestScalar.cs +++ b/Ryujinx.Tests/Cpu/CpuTestScalar.cs @@ -5,24 +5,52 @@ namespace Ryujinx.Tests.Cpu { public class CpuTestScalar : CpuTest { - [TestCase(0x00000000u, 0x80000000u, 0x00000000u)] - [TestCase(0x80000000u, 0x00000000u, 0x00000000u)] - [TestCase(0x80000000u, 0x80000000u, 0x80000000u)] - [TestCase(0x3DCCCCCDu, 0x3C9623B1u, 0x3DCCCCCDu)] - [TestCase(0x8BA98D27u, 0x00000076u, 0x00000076u)] - [TestCase(0x807FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu)] - [TestCase(0x7F7FFFFFu, 0x807FFFFFu, 0x7F7FFFFFu)] - [TestCase(0x7FC00000u, 0x3F800000u, 0x7FC00000u)] - [TestCase(0x3F800000u, 0x7FC00000u, 0x7FC00000u)] - [TestCase(0x7F800001u, 0x7FC00042u, 0x7FC00001u, Ignore = "NaN test.")] - [TestCase(0x7FC00042u, 0x7F800001u, 0x7FC00001u, Ignore = "NaN test.")] - [TestCase(0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Au, Ignore = "NaN test.")] - public void Fmax_S(uint A, uint B, uint Result) + [TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)] + [TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000000000000ul)] + [TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)] + [TestCase(0x1E224820u, 0x0000000080000000ul, 0x000000003DCCCCCDul, 0x000000003DCCCCCDul)] + [TestCase(0x1E224820u, 0x000000003DCCCCCDul, 0x000000003C9623B1ul, 0x000000003DCCCCCDul)] + [TestCase(0x1E224820u, 0x000000008BA98D27ul, 0x0000000000000076ul, 0x0000000000000076ul)] + [TestCase(0x1E224820u, 0x00000000807FFFFFul, 0x000000007F7FFFFFul, 0x000000007F7FFFFFul)] + [TestCase(0x1E224820u, 0x000000007F7FFFFFul, 0x00000000807FFFFFul, 0x000000007F7FFFFFul)] + [TestCase(0x1E224820u, 0x000000007FC00000ul, 0x000000003F800000ul, 0x000000007FC00000ul)] + [TestCase(0x1E224820u, 0x000000003F800000ul, 0x000000007FC00000ul, 0x000000007FC00000ul)] + [TestCase(0x1E224820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul, Ignore = "NaN test.")] + [TestCase(0x1E224820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul, Ignore = "NaN test.")] + [TestCase(0x1E224820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul, Ignore = "NaN test.")] + [TestCase(0x1E624820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x0000000000000000ul)] + [TestCase(0x1E624820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x0000000000000000ul)] + [TestCase(0x1E624820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)] + [TestCase(0x1E624820u, 0x8000000000000000ul, 0x3FF3333333333333ul, 0x3FF3333333333333ul)] + public void Fmax_S(uint Opcode, ulong A, ulong B, ulong Result) { // FMAX S0, S1, S2 - uint Opcode = 0x1E224820; - AThreadState ThreadState = SingleOpcode(Opcode, V1: new AVec { W0 = A }, V2: new AVec { W0 = B }); - Assert.AreEqual(Result, ThreadState.V0.W0); + AThreadState ThreadState = SingleOpcode(Opcode, V1: new AVec { X0 = A }, V2: new AVec { X0 = B }); + Assert.AreEqual(Result, ThreadState.V0.X0); + } + + [TestCase(0x1E225820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000080000000ul)] + [TestCase(0x1E225820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000080000000ul)] + [TestCase(0x1E225820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)] + [TestCase(0x1E225820u, 0x0000000080000000ul, 0x000000003DCCCCCDul, 0x0000000080000000ul)] + [TestCase(0x1E225820u, 0x000000003DCCCCCDul, 0x000000003C9623B1ul, 0x000000003C9623B1ul)] + [TestCase(0x1E225820u, 0x000000008BA98D27ul, 0x0000000000000076ul, 0x000000008BA98D27ul)] + [TestCase(0x1E225820u, 0x00000000807FFFFFul, 0x000000007F7FFFFFul, 0x00000000807FFFFFul)] + [TestCase(0x1E225820u, 0x000000007F7FFFFFul, 0x00000000807FFFFFul, 0x00000000807FFFFFul)] + [TestCase(0x1E225820u, 0x000000007FC00000ul, 0x000000003F800000ul, 0x000000007FC00000ul)] + [TestCase(0x1E225820u, 0x000000003F800000ul, 0x000000007FC00000ul, 0x000000007FC00000ul)] + [TestCase(0x1E225820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul, Ignore = "NaN test.")] + [TestCase(0x1E225820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul, Ignore = "NaN test.")] + [TestCase(0x1E225820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul, Ignore = "NaN test.")] + [TestCase(0x1E625820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)] + [TestCase(0x1E625820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x8000000000000000ul)] + [TestCase(0x1E625820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)] + [TestCase(0x1E625820u, 0x8000000000000000ul, 0x3FF3333333333333ul, 0x8000000000000000ul)] + public void Fmin_S(uint Opcode, ulong A, ulong B, ulong Result) + { + // FMIN S0, S1, S2 + AThreadState ThreadState = SingleOpcode(Opcode, V1: new AVec { X0 = A }, V2: new AVec { X0 = B }); + Assert.AreEqual(Result, ThreadState.V0.X0); } } } diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs index ba82be31b..f32fe398d 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs @@ -45,6 +45,58 @@ namespace Ryujinx.Tests.Cpu }); } + [TestCase(0x80000000u, 0x80000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u)] + [TestCase(0x00000000u, 0x00000000u, 0x80000000u, 0x80000000u, 0x00000000u, 0x00000000u)] + [TestCase(0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u)] + [TestCase(0x80000000u, 0x80000000u, 0x3DCCCCCDu, 0x3DCCCCCDu, 0x3DCCCCCDu, 0x3DCCCCCDu)] + [TestCase(0x3DCCCCCDu, 0x3DCCCCCDu, 0x3C9623B1u, 0x3C9623B1u, 0x3DCCCCCDu, 0x3DCCCCCDu)] + [TestCase(0x8BA98D27u, 0x8BA98D27u, 0x00000076u, 0x00000076u, 0x00000076u, 0x00000076u)] + [TestCase(0x807FFFFFu, 0x807FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu)] + [TestCase(0x7F7FFFFFu, 0x7F7FFFFFu, 0x807FFFFFu, 0x807FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu)] + [TestCase(0x7FC00000u, 0x7FC00000u, 0x3F800000u, 0x3F800000u, 0x7FC00000u, 0x7FC00000u)] + [TestCase(0x3F800000u, 0x3F800000u, 0x7FC00000u, 0x7FC00000u, 0x7FC00000u, 0x7FC00000u)] + [TestCase(0x7F800001u, 0x7F800001u, 0x7FC00042u, 0x7FC00042u, 0x7FC00001u, 0x7FC00001u, Ignore = "NaN test.")] + [TestCase(0x7FC00042u, 0x7FC00042u, 0x7F800001u, 0x7F800001u, 0x7FC00001u, 0x7FC00001u, Ignore = "NaN test.")] + [TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au, Ignore = "NaN test.")] + public void Fmax_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1) + { + uint Opcode = 0x4E22F420; + AVec V1 = new AVec { X0 = A, X1 = B }; + AVec V2 = new AVec { X0 = C, X1 = D }; + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + Assert.Multiple(() => + { + Assert.AreEqual(Result0, ThreadState.V0.X0); + Assert.AreEqual(Result1, ThreadState.V0.X1); + }); + } + + [TestCase(0x80000000u, 0x80000000u, 0x00000000u, 0x00000000u, 0x80000000u, 0x80000000u)] + [TestCase(0x00000000u, 0x00000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u)] + [TestCase(0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u)] + [TestCase(0x80000000u, 0x80000000u, 0x3DCCCCCDu, 0x3DCCCCCDu, 0x80000000u, 0x80000000u)] + [TestCase(0x3DCCCCCDu, 0x3DCCCCCDu, 0x3C9623B1u, 0x3C9623B1u, 0x3C9623B1u, 0x3C9623B1u)] + [TestCase(0x8BA98D27u, 0x8BA98D27u, 0x00000076u, 0x00000076u, 0x8BA98D27u, 0x8BA98D27u)] + [TestCase(0x807FFFFFu, 0x807FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu, 0x807FFFFFu, 0x807FFFFFu)] + [TestCase(0x7F7FFFFFu, 0x7F7FFFFFu, 0x807FFFFFu, 0x807FFFFFu, 0x807FFFFFu, 0x807FFFFFu)] + [TestCase(0x7FC00000u, 0x7FC00000u, 0x3F800000u, 0x3F800000u, 0x7FC00000u, 0x7FC00000u)] + [TestCase(0x3F800000u, 0x3F800000u, 0x7FC00000u, 0x7FC00000u, 0x7FC00000u, 0x7FC00000u)] + [TestCase(0x7F800001u, 0x7F800001u, 0x7FC00042u, 0x7FC00042u, 0x7FC00001u, 0x7FC00001u, Ignore = "NaN test.")] + [TestCase(0x7FC00042u, 0x7FC00042u, 0x7F800001u, 0x7F800001u, 0x7FC00001u, 0x7FC00001u, Ignore = "NaN test.")] + [TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au, Ignore = "NaN test.")] + public void Fmin_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1) + { + uint Opcode = 0x4EA2F420; + AVec V1 = new AVec { X0 = A, X1 = B }; + AVec V2 = new AVec { X0 = C, X1 = D }; + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + Assert.Multiple(() => + { + Assert.AreEqual(Result0, ThreadState.V0.X0); + Assert.AreEqual(Result1, ThreadState.V0.X1); + }); + } + [Test, Description("fmul s6, s1, v0.s[2]")] public void Fmul_Se([Random(10)] float A, [Random(10)] float B) {