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Add FMaxNmV & FMinNmV Inst.s with Test. (#1279)
Successful unit testing on Windows (debug and release mode).
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5 changed files with 71 additions and 0 deletions
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@ -332,11 +332,13 @@ namespace ARMeilleure.Decoders
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SetA64("0>0011100<1xxxxx111101xxxxxxxxxx", InstName.Fmax_V, InstEmit.Fmax_V, typeof(OpCodeSimdReg));
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SetA64("0>0011100<1xxxxx111101xxxxxxxxxx", InstName.Fmax_V, InstEmit.Fmax_V, typeof(OpCodeSimdReg));
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SetA64("000111100x1xxxxx011010xxxxxxxxxx", InstName.Fmaxnm_S, InstEmit.Fmaxnm_S, typeof(OpCodeSimdReg));
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SetA64("000111100x1xxxxx011010xxxxxxxxxx", InstName.Fmaxnm_S, InstEmit.Fmaxnm_S, typeof(OpCodeSimdReg));
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SetA64("0>0011100<1xxxxx110001xxxxxxxxxx", InstName.Fmaxnm_V, InstEmit.Fmaxnm_V, typeof(OpCodeSimdReg));
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SetA64("0>0011100<1xxxxx110001xxxxxxxxxx", InstName.Fmaxnm_V, InstEmit.Fmaxnm_V, typeof(OpCodeSimdReg));
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SetA64("0110111000110000110010xxxxxxxxxx", InstName.Fmaxnmv_V, InstEmit.Fmaxnmv_V, typeof(OpCodeSimd));
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SetA64("0>1011100<1xxxxx111101xxxxxxxxxx", InstName.Fmaxp_V, InstEmit.Fmaxp_V, typeof(OpCodeSimdReg));
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SetA64("0>1011100<1xxxxx111101xxxxxxxxxx", InstName.Fmaxp_V, InstEmit.Fmaxp_V, typeof(OpCodeSimdReg));
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SetA64("000111100x1xxxxx010110xxxxxxxxxx", InstName.Fmin_S, InstEmit.Fmin_S, typeof(OpCodeSimdReg));
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SetA64("000111100x1xxxxx010110xxxxxxxxxx", InstName.Fmin_S, InstEmit.Fmin_S, typeof(OpCodeSimdReg));
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SetA64("0>0011101<1xxxxx111101xxxxxxxxxx", InstName.Fmin_V, InstEmit.Fmin_V, typeof(OpCodeSimdReg));
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SetA64("0>0011101<1xxxxx111101xxxxxxxxxx", InstName.Fmin_V, InstEmit.Fmin_V, typeof(OpCodeSimdReg));
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SetA64("000111100x1xxxxx011110xxxxxxxxxx", InstName.Fminnm_S, InstEmit.Fminnm_S, typeof(OpCodeSimdReg));
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SetA64("000111100x1xxxxx011110xxxxxxxxxx", InstName.Fminnm_S, InstEmit.Fminnm_S, typeof(OpCodeSimdReg));
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SetA64("0>0011101<1xxxxx110001xxxxxxxxxx", InstName.Fminnm_V, InstEmit.Fminnm_V, typeof(OpCodeSimdReg));
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SetA64("0>0011101<1xxxxx110001xxxxxxxxxx", InstName.Fminnm_V, InstEmit.Fminnm_V, typeof(OpCodeSimdReg));
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SetA64("0110111010110000110010xxxxxxxxxx", InstName.Fminnmv_V, InstEmit.Fminnmv_V, typeof(OpCodeSimd));
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SetA64("0>1011101<1xxxxx111101xxxxxxxxxx", InstName.Fminp_V, InstEmit.Fminp_V, typeof(OpCodeSimdReg));
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SetA64("0>1011101<1xxxxx111101xxxxxxxxxx", InstName.Fminp_V, InstEmit.Fminp_V, typeof(OpCodeSimdReg));
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SetA64("010111111xxxxxxx0001x0xxxxxxxxxx", InstName.Fmla_Se, InstEmit.Fmla_Se, typeof(OpCodeSimdRegElemF));
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SetA64("010111111xxxxxxx0001x0xxxxxxxxxx", InstName.Fmla_Se, InstEmit.Fmla_Se, typeof(OpCodeSimdRegElemF));
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SetA64("0>0011100<1xxxxx110011xxxxxxxxxx", InstName.Fmla_V, InstEmit.Fmla_V, typeof(OpCodeSimdReg));
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SetA64("0>0011100<1xxxxx110011xxxxxxxxxx", InstName.Fmla_V, InstEmit.Fmla_V, typeof(OpCodeSimdReg));
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@ -534,6 +534,14 @@ namespace ARMeilleure.Instructions
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}
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}
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}
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}
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public static void Fmaxnmv_V(ArmEmitterContext context)
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{
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EmitVectorAcrossVectorOpF(context, (op1, op2) =>
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{
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return context.Call(new _F32_F32_F32(SoftFloat32.FPMaxNum), op1, op2);
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});
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}
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public static void Fmaxp_V(ArmEmitterContext context)
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public static void Fmaxp_V(ArmEmitterContext context)
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{
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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if (Optimizations.FastFP && Optimizations.UseSse2)
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@ -609,6 +617,14 @@ namespace ARMeilleure.Instructions
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}
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}
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}
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}
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public static void Fminnmv_V(ArmEmitterContext context)
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{
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EmitVectorAcrossVectorOpF(context, (op1, op2) =>
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{
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return context.Call(new _F32_F32_F32(SoftFloat32.FPMinNum), op1, op2);
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});
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}
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public static void Fminp_V(ArmEmitterContext context)
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public static void Fminp_V(ArmEmitterContext context)
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{
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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if (Optimizations.FastFP && Optimizations.UseSse2)
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@ -1103,6 +1103,26 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVec(op.Rd), d);
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context.Copy(GetVec(op.Rd), d);
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}
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}
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public static void EmitVectorAcrossVectorOpF(ArmEmitterContext context, Func2I emit)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Debug.Assert((op.Size & 1) == 0 && op.RegisterSize == RegisterSize.Simd128);
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Operand res = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), 0);
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for (int index = 1; index < 4; index++)
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{
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Operand n = context.VectorExtract(OperandType.FP32, GetVec(op.Rn), index);
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res = emit(res, n);
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}
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Operand d = context.VectorInsert(context.VectorZero(), res, 0);
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context.Copy(GetVec(op.Rd), d);
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}
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public static void EmitVectorPairwiseOpF(ArmEmitterContext context, Func2I emit)
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public static void EmitVectorPairwiseOpF(ArmEmitterContext context, Func2I emit)
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{
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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@ -212,11 +212,13 @@ namespace ARMeilleure.Instructions
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Fmax_V,
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Fmax_V,
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Fmaxnm_S,
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Fmaxnm_S,
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Fmaxnm_V,
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Fmaxnm_V,
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Fmaxnmv_V,
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Fmaxp_V,
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Fmaxp_V,
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Fmin_S,
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Fmin_S,
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Fmin_V,
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Fmin_V,
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Fminnm_S,
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Fminnm_S,
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Fminnm_V,
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Fminnm_V,
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Fminnmv_V,
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Fminp_V,
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Fminp_V,
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Fmla_Se,
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Fmla_Se,
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Fmla_V,
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Fmla_V,
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@ -913,6 +913,15 @@ namespace Ryujinx.Tests.Cpu
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};
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};
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}
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}
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private static uint[] _F_Max_Min_Nm_V_V_4SS_()
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{
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return new uint[]
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{
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0x6E30C800u, // FMAXNMV S0, V0.4S
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0x6EB0C800u // FMINNMV S0, V0.4S
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};
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}
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private static uint[] _F_Mov_Ftoi_SW_()
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private static uint[] _F_Mov_Ftoi_SW_()
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{
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{
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return new uint[]
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return new uint[]
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@ -2142,6 +2151,28 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Test, Pairwise] [Explicit]
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public void F_Max_Min_Nm_V_V_4SS([ValueSource("_F_Max_Min_Nm_V_V_4SS_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_2S_F_")] ulong z,
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[ValueSource("_2S_F_")] ulong a)
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{
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a);
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int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
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int fpcr = rnd & (1 << (int)Fpcr.Fz);
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fpcr |= rnd & (1 << (int)Fpcr.Dn);
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SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
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CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc);
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}
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[Test, Pairwise] [Explicit]
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[Test, Pairwise] [Explicit]
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public void F_Mov_Ftoi_SW([ValueSource("_F_Mov_Ftoi_SW_")] uint opcodes,
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public void F_Mov_Ftoi_SW([ValueSource("_F_Mov_Ftoi_SW_")] uint opcodes,
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[Values(0u, 31u)] uint rd,
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[Values(0u, 31u)] uint rd,
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