From a4ff0d34848416a68dff9f165bb90afae7a4fd20 Mon Sep 17 00:00:00 2001 From: MS-DOS1999 Date: Sun, 25 Feb 2018 02:50:58 +0100 Subject: [PATCH] Update ADC test, add WZR/WSP, ADCS, SBCS test (#37) * add 'ADC 32bit and Overflow' test * Add WZR/WSP tests * fix ADC and ADDS * add ADCS test * add SBCS test * indent my code and delete comment * '/' <- i hate you x) * remove spacebar char * remove false tab --- Ryujinx.Tests/Cpu/CpuTest.cs | 7 ++-- Ryujinx.Tests/Cpu/CpuTestAlu.cs | 64 +++++++++++++++++++++++++++++---- 2 files changed, 62 insertions(+), 9 deletions(-) diff --git a/Ryujinx.Tests/Cpu/CpuTest.cs b/Ryujinx.Tests/Cpu/CpuTest.cs index 92c74e443..7af2d55d0 100644 --- a/Ryujinx.Tests/Cpu/CpuTest.cs +++ b/Ryujinx.Tests/Cpu/CpuTest.cs @@ -57,13 +57,14 @@ namespace Ryujinx.Tests.Cpu Position += 4; } - protected void SetThreadState(ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, + protected void SetThreadState(ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X31 = 0, AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec), bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false) { Thread.ThreadState.X0 = X0; Thread.ThreadState.X1 = X1; Thread.ThreadState.X2 = X2; + Thread.ThreadState.X31 = X31; Thread.ThreadState.V0 = V0; Thread.ThreadState.V1 = V1; Thread.ThreadState.V2 = V2; @@ -91,14 +92,14 @@ namespace Ryujinx.Tests.Cpu } protected AThreadState SingleOpcode(uint Opcode, - ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, + ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X31 = 0, AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec), bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false) { this.Opcode(Opcode); this.Opcode(0xD4200000); // BRK #0 this.Opcode(0xD65F03C0); // RET - SetThreadState(X0, X1, X2, V0, V1, V2, Overflow, Carry, Zero, Negative); + SetThreadState(X0, X1, X2, X31, V0, V1, V2, Overflow, Carry, Zero, Negative); ExecuteOpcodes(); return GetThreadState(); diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/Ryujinx.Tests/Cpu/CpuTestAlu.cs index b73212ac5..0445c97ab 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAlu.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAlu.cs @@ -5,12 +5,31 @@ namespace Ryujinx.Tests.Cpu { public class CpuTestAlu : CpuTest { - [TestCase(2u, 3u, 6ul, true)] - [TestCase(2u, 3u, 5ul, false)] - public void Adc(uint A, uint B, ulong Result, bool CarryTest) + [TestCase(0x9A020020u, 2u, 3u, true, 6u)] + [TestCase(0x9A020020u, 2u, 3u, false, 5u)] + [TestCase(0x1A020020u, 2u, 3u, true, 6u)] + [TestCase(0x1A020020u, 2u, 3u, false, 5u)] + [TestCase(0x1A020020u, 0xFFFFFFFFu, 0x2u, false, 0x1u)] + public void Adc(uint Opcode, uint A, uint B, bool CarryState, uint Result) { - // ADC X0, X1, X2 - AThreadState ThreadState = SingleOpcode(0x9A020020, X1: A, X2: B, Carry: CarryTest); + // ADC (X0/W0), (X1/W1), (X2/W2) + AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState); + Assert.AreEqual(Result, ThreadState.X0); + } + + [TestCase(0x3A020020u, 2u, 3u, false, false, false, 5u)] + [TestCase(0x3A020020u, 2u, 3u, true, false, false, 6u)] + [TestCase(0xBA020020u, 2u, 3u, false, false, false, 5u)] + [TestCase(0xBA020020u, 2u, 3u, true, false, false, 6u)] + [TestCase(0x3A020020u, 0xFFFFFFFEu, 0x1u, true, true, true, 0x0u)] + public void Adcs(uint Opcode, uint A, uint B, bool CarryState, bool Zero, bool Carry, uint Result) + { + //ADCS (X0/W0), (X1, W1), (X2/W2) + AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState); + Assert.IsFalse(ThreadState.Negative); + Assert.IsFalse(ThreadState.Overflow); + Assert.AreEqual(Zero, ThreadState.Zero); + Assert.AreEqual(Carry, ThreadState.Carry); Assert.AreEqual(Result, ThreadState.X0); } @@ -22,7 +41,23 @@ namespace Ryujinx.Tests.Cpu Assert.AreEqual(3, ThreadState.X0); } - [TestCase(0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFul, true, false)] + [TestCase(2u, false, false)] + [TestCase(5u, false, false)] + [TestCase(7u, false, false)] + [TestCase(0xFFFFFFFFu, false, true )] + [TestCase(0xFFFFFFFBu, true, true )] + public void Adds(uint A, bool Zero, bool Carry) + { + //ADDS WZR, WSP, #5 + AThreadState ThreadState = SingleOpcode(0x310017FF, X31: A); + Assert.IsFalse(ThreadState.Negative); + Assert.AreEqual(Zero, ThreadState.Zero); + Assert.AreEqual(Carry, ThreadState.Carry); + Assert.IsFalse(ThreadState.Overflow); + Assert.AreEqual(A, ThreadState.X31); + } + + [TestCase(0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFul, true, false)] [TestCase(0xFFFFFFFFu, 0x00000000u, 0x00000000ul, false, true)] [TestCase(0x12345678u, 0x7324A993u, 0x12240010ul, false, false)] public void Ands(uint A, uint B, ulong Result, bool Negative, bool Zero) @@ -67,5 +102,22 @@ namespace Ryujinx.Tests.Cpu AThreadState ThreadState = SingleOpcode(0x5AC00821, X1: 0x12345678); Assert.AreEqual(0x78563412, ThreadState.X1); } + + [TestCase(0x7A020020u, 4u, 2u, false, false, false, true, 1u)] + [TestCase(0x7A020020u, 4u, 2u, true, false, false, true, 2u)] + [TestCase(0xFA020020u, 4u, 2u, false, false, false, true, 1u)] + [TestCase(0xFA020020u, 4u, 2u, true, false, false, true, 2u)] + [TestCase(0x7A020020u, 4u, 4u, false, true, false, false, 0xFFFFFFFFu)] + [TestCase(0x7A020020u, 4u, 4u, true, false, true, true, 0x0u)] + public void Sbcs(uint Opcode, uint A, uint B, bool CarryState, bool Negative, bool Zero, bool Carry, uint Result) + { + //SBCS (X0/W0), (X1, W1), (X2/W2) + AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState); + Assert.AreEqual(Negative, ThreadState.Negative); + Assert.IsFalse(ThreadState.Overflow); + Assert.AreEqual(Zero, ThreadState.Zero); + Assert.AreEqual(Carry, ThreadState.Carry); + Assert.AreEqual(Result, ThreadState.X0); + } } }