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https://github.com/Ryujinx/Ryujinx.git
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Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104)
* Update AOpCodeTable.cs * Update AInstEmitSimdLogical.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs
This commit is contained in:
LDj3SNuD
gdkchan
parent
a38a72b062
commit
a5ad1e9a06
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@ -148,6 +148,8 @@ namespace ChocolArm64
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Set("0x101110111xxxxx000111xxxxxxxxxx", AInstEmit.Bif_V, typeof(AOpCodeSimdReg));
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Set("0x101110101xxxxx000111xxxxxxxxxx", AInstEmit.Bit_V, typeof(AOpCodeSimdReg));
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Set("0x101110011xxxxx000111xxxxxxxxxx", AInstEmit.Bsl_V, typeof(AOpCodeSimdReg));
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Set("0x001110<<100000010010xxxxxxxxxx", AInstEmit.Cls_V, typeof(AOpCodeSimd));
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Set("0x101110<<100000010010xxxxxxxxxx", AInstEmit.Clz_V, typeof(AOpCodeSimd));
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Set("0>101110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimdReg));
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Set("0>001110<<100000100110xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimd));
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Set("0>001110<<1xxxxx001111xxxxxxxxxx", AInstEmit.Cmge_V, typeof(AOpCodeSimdReg));
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@ -289,6 +291,7 @@ namespace ChocolArm64
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Set("0111111011100000101110xxxxxxxxxx", AInstEmit.Neg_S, typeof(AOpCodeSimd));
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Set("0>101110<<100000101110xxxxxxxxxx", AInstEmit.Neg_V, typeof(AOpCodeSimd));
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Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd));
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Set("0x001110111xxxxx000111xxxxxxxxxx", AInstEmit.Orn_V, typeof(AOpCodeSimdReg));
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Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg));
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Set("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm));
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Set("0x101110<<1xxxxx010000xxxxxxxxxx", AInstEmit.Raddhn_V, typeof(AOpCodeSimdReg));
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@ -106,14 +106,9 @@ namespace ChocolArm64.Instruction
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Context.EmitLdintzr(Op.Rn);
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if (Op.RegisterSize == ARegisterSize.Int32)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingSigns32));
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}
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else
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingSigns64));
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}
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Context.EmitLdc_I4(Op.RegisterSize == ARegisterSize.Int32 ? 32 : 64);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingSigns));
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Context.EmitStintzr(Op.Rd);
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}
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@ -124,14 +119,9 @@ namespace ChocolArm64.Instruction
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Context.EmitLdintzr(Op.Rn);
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if (Op.RegisterSize == ARegisterSize.Int32)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingZeros32));
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}
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else
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingZeros64));
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}
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Context.EmitLdc_I4(Op.RegisterSize == ARegisterSize.Int32 ? 32 : 64);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingZeros));
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Context.EmitStintzr(Op.Rd);
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}
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@ -109,6 +109,43 @@ namespace ChocolArm64.Instruction
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EmitScalarSet(Context, Op.Rd, Op.Size);
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}
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public static void Cls_V(AILEmitterCtx Context)
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{
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MethodInfo MthdInfo = typeof(ASoftFallback).GetMethod(nameof(ASoftFallback.CountLeadingSigns));
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EmitCountLeadingBits(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Clz_V(AILEmitterCtx Context)
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{
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MethodInfo MthdInfo = typeof(ASoftFallback).GetMethod(nameof(ASoftFallback.CountLeadingZeros));
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EmitCountLeadingBits(Context, () => Context.EmitCall(MthdInfo));
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}
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private static void EmitCountLeadingBits(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
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Context.EmitLdc_I4(8 << Op.Size);
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Emit();
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Cnt_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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@ -103,6 +103,15 @@ namespace ChocolArm64.Instruction
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EmitVectorUnaryOpZx(Context, () => Context.Emit(OpCodes.Not));
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}
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public static void Orn_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpZx(Context, () =>
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{
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Context.Emit(OpCodes.Not);
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Context.Emit(OpCodes.Or);
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});
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}
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public static void Orr_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Or));
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@ -136,4 +145,4 @@ namespace ChocolArm64.Instruction
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}
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}
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}
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}
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}
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@ -20,18 +20,12 @@ namespace ChocolArm64.Instruction
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Context.EmitCall(typeof(ASoftFallback), MthdName);
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}
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public static uint CountLeadingSigns32(uint Value) => (uint)CountLeadingSigns(Value, 32);
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public static ulong CountLeadingSigns64(ulong Value) => (ulong)CountLeadingSigns(Value, 64);
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private static ulong CountLeadingSigns(ulong Value, int Size)
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public static ulong CountLeadingSigns(ulong Value, int Size)
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{
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return CountLeadingZeros((Value >> 1) ^ Value, Size - 1);
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}
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public static uint CountLeadingZeros32(uint Value) => (uint)CountLeadingZeros(Value, 32);
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public static ulong CountLeadingZeros64(ulong Value) => (ulong)CountLeadingZeros(Value, 64);
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private static ulong CountLeadingZeros(ulong Value, int Size)
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public static ulong CountLeadingZeros(ulong Value, int Size)
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{
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int HighBit = Size - 1;
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@ -179,6 +179,90 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Description("CLS <Vd>.<T>, <Vn>.<T>")]
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public void Cls_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
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{
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uint Opcode = 0x0E204820; // CLS V0.8B, V1.8B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.V(1, new Bits(A));
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SimdFp.Cls_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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}
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[Test, Pairwise, Description("CLS <Vd>.<T>, <Vn>.<T>")]
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public void Cls_V_16B_8H_4S([ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
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[ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
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{
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uint Opcode = 0x4E204820; // CLS V0.16B, V1.16B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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SimdFp.Cls_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
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public void Clz_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
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{
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uint Opcode = 0x2E204820; // CLZ V0.8B, V1.8B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.V(1, new Bits(A));
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SimdFp.Clz_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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}
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[Test, Pairwise, Description("CLZ <Vd>.<T>, <Vn>.<T>")]
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public void Clz_V_16B_8H_4S([ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
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[ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
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{
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uint Opcode = 0x6E204820; // CLZ V0.16B, V1.16B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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SimdFp.Clz_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("NEG <V><d>, <V><n>")]
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public void Neg_S_D([ValueSource("_1D_")] [Random(1)] ulong A)
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{
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@ -26,6 +26,20 @@ namespace Ryujinx.Tests.Cpu
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H2S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _8B4H2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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@ -42,14 +56,6 @@ namespace Ryujinx.Tests.Cpu
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0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H2S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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[Test, Description("ADD <V><d>, <V><n>, <V><m>")]
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@ -231,6 +237,349 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Description("AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void And_V_8B([ValueSource("_8B_")] [Random(1)] ulong A,
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[ValueSource("_8B_")] [Random(1)] ulong B)
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{
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uint Opcode = 0x0E221C20; // AND V0.8B, V1.8B, V2.8B
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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AVec V2 = new AVec { X0 = B };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.V(1, new Bits(A));
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AArch64.V(2, new Bits(B));
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SimdFp.And_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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}
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[Test, Pairwise, Description("AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void And_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
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[ValueSource("_8B_")] [Random(1)] ulong A1,
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[ValueSource("_8B_")] [Random(1)] ulong B0,
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[ValueSource("_8B_")] [Random(1)] ulong B1)
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{
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uint Opcode = 0x4E221C20; // AND V0.16B, V1.16B, V2.16B
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Bits Op = new Bits(Opcode);
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
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AArch64.Vpart(2, 1, new Bits(B1));
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SimdFp.And_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Bic_V_8B([ValueSource("_8B_")] [Random(1)] ulong A,
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[ValueSource("_8B_")] [Random(1)] ulong B)
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{
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uint Opcode = 0x0E621C20; // BIC V0.8B, V1.8B, V2.8B
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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AVec V2 = new AVec { X0 = B };
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
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AArch64.V(1, new Bits(A));
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AArch64.V(2, new Bits(B));
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SimdFp.Bic_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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}
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[Test, Pairwise, Description("BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
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public void Bic_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
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[ValueSource("_8B_")] [Random(1)] ulong A1,
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[ValueSource("_8B_")] [Random(1)] ulong B0,
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[ValueSource("_8B_")] [Random(1)] ulong B1)
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{
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uint Opcode = 0x4E621C20; // BIC V0.16B, V1.16B, V2.16B
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Bits Op = new Bits(Opcode);
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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AArch64.Vpart(2, 0, new Bits(B0));
|
||||
AArch64.Vpart(2, 1, new Bits(B1));
|
||||
SimdFp.Bic_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Bif_V_8B([ValueSource("_8B_")] [Random(1)] ulong _Z,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B)
|
||||
{
|
||||
uint Opcode = 0x2EE21C20; // BIF V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = _Z, X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(_Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
SimdFp.Bif_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Bif_V_16B([ValueSource("_8B_")] [Random(1)] ulong _Z0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong _Z1,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A1,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B1)
|
||||
{
|
||||
uint Opcode = 0x6EE21C20; // BIF V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = _Z0, X1 = _Z1 };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(_Z0));
|
||||
AArch64.Vpart(0, 1, new Bits(_Z1));
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
AArch64.Vpart(1, 1, new Bits(A1));
|
||||
AArch64.Vpart(2, 0, new Bits(B0));
|
||||
AArch64.Vpart(2, 1, new Bits(B1));
|
||||
SimdFp.Bif_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Bit_V_8B([ValueSource("_8B_")] [Random(1)] ulong _Z,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B)
|
||||
{
|
||||
uint Opcode = 0x2EA21C20; // BIT V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = _Z, X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(_Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
SimdFp.Bit_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Bit_V_16B([ValueSource("_8B_")] [Random(1)] ulong _Z0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong _Z1,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A1,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B1)
|
||||
{
|
||||
uint Opcode = 0x6EA21C20; // BIT V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = _Z0, X1 = _Z1 };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(_Z0));
|
||||
AArch64.Vpart(0, 1, new Bits(_Z1));
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
AArch64.Vpart(1, 1, new Bits(A1));
|
||||
AArch64.Vpart(2, 0, new Bits(B0));
|
||||
AArch64.Vpart(2, 1, new Bits(B1));
|
||||
SimdFp.Bit_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Bsl_V_8B([ValueSource("_8B_")] [Random(1)] ulong _Z,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B)
|
||||
{
|
||||
uint Opcode = 0x2E621C20; // BSL V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = _Z, X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(_Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
SimdFp.Bsl_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Bsl_V_16B([ValueSource("_8B_")] [Random(1)] ulong _Z0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong _Z1,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A1,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B1)
|
||||
{
|
||||
uint Opcode = 0x6E621C20; // BSL V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = _Z0, X1 = _Z1 };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(_Z0));
|
||||
AArch64.Vpart(0, 1, new Bits(_Z1));
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
AArch64.Vpart(1, 1, new Bits(A1));
|
||||
AArch64.Vpart(2, 0, new Bits(B0));
|
||||
AArch64.Vpart(2, 1, new Bits(B1));
|
||||
SimdFp.Bsl_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Orn_V_8B([ValueSource("_8B_")] [Random(1)] ulong A,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B)
|
||||
{
|
||||
uint Opcode = 0x0EE21C20; // ORN V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
SimdFp.Orn_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Orn_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A1,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B1)
|
||||
{
|
||||
uint Opcode = 0x4EE21C20; // ORN V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
AArch64.Vpart(1, 1, new Bits(A1));
|
||||
AArch64.Vpart(2, 0, new Bits(B0));
|
||||
AArch64.Vpart(2, 1, new Bits(B1));
|
||||
SimdFp.Orn_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Orr_V_8B([ValueSource("_8B_")] [Random(1)] ulong A,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B)
|
||||
{
|
||||
uint Opcode = 0x0EA21C20; // ORR V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
SimdFp.Orr_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Orr_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong A1,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B0,
|
||||
[ValueSource("_8B_")] [Random(1)] ulong B1)
|
||||
{
|
||||
uint Opcode = 0x4EA21C20; // ORR V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
AArch64.Vpart(1, 1, new Bits(A1));
|
||||
AArch64.Vpart(2, 0, new Bits(B0));
|
||||
AArch64.Vpart(2, 1, new Bits(B1));
|
||||
SimdFp.Orr_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("RADDHN{2} <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>")]
|
||||
public void Raddhn_V_8H8B_4S4H_2D2S([ValueSource("_4H2S1D_")] [Random(1)] ulong A0,
|
||||
[ValueSource("_4H2S1D_")] [Random(1)] ulong A1,
|
||||
|
|
|
|||
|
|
@ -1699,6 +1699,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
|
||||
BigInteger element;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
|
|
@ -1742,6 +1743,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
|
||||
BigInteger element;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
|
|
@ -1810,6 +1812,90 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, Reduce(op, operand, esize));
|
||||
}
|
||||
|
||||
// https://meriac.github.io/archex/A64_v83A_ISA/cls_advsimd.xml
|
||||
public static void Cls_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
bool U = false;
|
||||
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
CountOp countop = (U ? CountOp.CountOp_CLZ : CountOp.CountOp_CLS);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
|
||||
BigInteger count;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
if (countop == CountOp.CountOp_CLS)
|
||||
{
|
||||
count = (BigInteger)CountLeadingSignBits(Elem(operand, e, esize));
|
||||
}
|
||||
else
|
||||
{
|
||||
count = (BigInteger)CountLeadingZeroBits(Elem(operand, e, esize));
|
||||
}
|
||||
|
||||
Elem(result, e, esize, count.SubBigInteger(esize - 1, 0));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// https://meriac.github.io/archex/A64_v83A_ISA/clz_advsimd.xml
|
||||
public static void Clz_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
bool U = true;
|
||||
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
CountOp countop = (U ? CountOp.CountOp_CLZ : CountOp.CountOp_CLS);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
|
||||
BigInteger count;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
if (countop == CountOp.CountOp_CLS)
|
||||
{
|
||||
count = (BigInteger)CountLeadingSignBits(Elem(operand, e, esize));
|
||||
}
|
||||
else
|
||||
{
|
||||
count = (BigInteger)CountLeadingZeroBits(Elem(operand, e, esize));
|
||||
}
|
||||
|
||||
Elem(result, e, esize, count.SubBigInteger(esize - 1, 0));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// https://meriac.github.io/archex/A64_v83A_ISA/neg_advsimd.xml#NEG_asisdmisc_R
|
||||
public static void Neg_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
@ -1832,6 +1918,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
|
||||
BigInteger element;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
|
|
@ -1875,6 +1962,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
|
||||
BigInteger element;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
|
|
@ -2077,6 +2165,163 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// https://meriac.github.io/archex/A64_v83A_ISA/and_advsimd.xml
|
||||
public static void And_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
int datasize = (Q ? 128 : 64);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
|
||||
Bits result = AND(operand1, operand2);
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// https://meriac.github.io/archex/A64_v83A_ISA/bic_advsimd_reg.xml
|
||||
public static void Bic_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
int datasize = (Q ? 128 : 64);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
|
||||
operand2 = NOT(operand2);
|
||||
|
||||
Bits result = AND(operand1, operand2);
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// https://meriac.github.io/archex/A64_v83A_ISA/bif_advsimd.xml
|
||||
public static void Bif_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
int datasize = (Q ? 128 : 64);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits operand1;
|
||||
Bits operand3;
|
||||
Bits operand4 = V(datasize, n);
|
||||
|
||||
operand1 = V(datasize, d);
|
||||
operand3 = NOT(V(datasize, m));
|
||||
|
||||
V(d, EOR(operand1, AND(EOR(operand1, operand4), operand3)));
|
||||
}
|
||||
|
||||
// https://meriac.github.io/archex/A64_v83A_ISA/bit_advsimd.xml
|
||||
public static void Bit_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
int datasize = (Q ? 128 : 64);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits operand1;
|
||||
Bits operand3;
|
||||
Bits operand4 = V(datasize, n);
|
||||
|
||||
operand1 = V(datasize, d);
|
||||
operand3 = V(datasize, m);
|
||||
|
||||
V(d, EOR(operand1, AND(EOR(operand1, operand4), operand3)));
|
||||
}
|
||||
|
||||
// https://meriac.github.io/archex/A64_v83A_ISA/bsl_advsimd.xml
|
||||
public static void Bsl_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
int datasize = (Q ? 128 : 64);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits operand1;
|
||||
Bits operand3;
|
||||
Bits operand4 = V(datasize, n);
|
||||
|
||||
operand1 = V(datasize, m);
|
||||
operand3 = V(datasize, d);
|
||||
|
||||
V(d, EOR(operand1, AND(EOR(operand1, operand4), operand3)));
|
||||
}
|
||||
|
||||
// https://meriac.github.io/archex/A64_v83A_ISA/orn_advsimd.xml
|
||||
public static void Orn_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
int datasize = (Q ? 128 : 64);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
|
||||
operand2 = NOT(operand2);
|
||||
|
||||
Bits result = OR(operand1, operand2);
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// https://meriac.github.io/archex/A64_v83A_ISA/orr_advsimd_reg.xml
|
||||
public static void Orr_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
int datasize = (Q ? 128 : 64);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
|
||||
Bits result = OR(operand1, operand2);
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// https://meriac.github.io/archex/A64_v83A_ISA/raddhn_advsimd.xml
|
||||
public static void Raddhn_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -253,6 +253,11 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
}
|
||||
#endregion
|
||||
|
||||
#region "instrs/countop/"
|
||||
// #CountOp
|
||||
public enum CountOp {CountOp_CLZ, CountOp_CLS, CountOp_CNT};
|
||||
#endregion
|
||||
|
||||
#region "instrs/extendreg/"
|
||||
/* #impl-aarch64.DecodeRegExtend.1 */
|
||||
public static ExtendType DecodeRegExtend(Bits op)
|
||||
|
|
|
|||
Loading…
Reference in a new issue