diff --git a/ARMeilleure/Decoders/OpCodeTable.cs b/ARMeilleure/Decoders/OpCodeTable.cs
index 028a53772..c1ac83635 100644
--- a/ARMeilleure/Decoders/OpCodeTable.cs
+++ b/ARMeilleure/Decoders/OpCodeTable.cs
@@ -907,6 +907,7 @@ namespace ARMeilleure.Decoders
             SetA32("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla,    InstEmit32.Vnmla_S,  OpCode32SimdRegS.Create);
             SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls,    InstEmit32.Vnmls_S,  OpCode32SimdRegS.Create);
             SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul,    InstEmit32.Vnmul_S,  OpCode32SimdRegS.Create);
+            SetA32("111100100x11xxxxxxxx0001xxx1xxxx", InstName.Vorn,     InstEmit32.Vorn_I,   OpCode32SimdBinary.Create);
             SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr,     InstEmit32.Vorr_I,   OpCode32SimdBinary.Create);
             SetA32("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr,     InstEmit32.Vorr_II,  OpCode32SimdImm.Create);
             SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd,    InstEmit32.Vpadd_I,  OpCode32SimdReg.Create);
diff --git a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
index 2d6bf481a..48bf18bc7 100644
--- a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
@@ -115,6 +115,24 @@ namespace ARMeilleure.Instructions
             }
         }
 
+        public static void Vorn_I(ArmEmitterContext context)
+        {
+            if (Optimizations.UseSse2)
+            {
+                Operand mask = context.VectorOne();
+
+                EmitVectorBinaryOpSimd32(context, (n, m) =>
+                {
+                    m = context.AddIntrinsic(Intrinsic.X86Pandn, m, mask);
+                    return context.AddIntrinsic(Intrinsic.X86Por, n, m);
+                });
+            }
+            else
+            {
+                EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseOr(op1, context.BitwiseNot(op2)));
+            }
+        }
+
         public static void Vorr_I(ArmEmitterContext context)
         {
             if (Optimizations.UseSse2)
diff --git a/ARMeilleure/Instructions/InstName.cs b/ARMeilleure/Instructions/InstName.cs
index fe7644a91..9b4e89618 100644
--- a/ARMeilleure/Instructions/InstName.cs
+++ b/ARMeilleure/Instructions/InstName.cs
@@ -605,6 +605,7 @@ namespace ARMeilleure.Instructions
         Vnmul,
         Vnmla,
         Vnmls,
+        Vorn,
         Vorr,
         Vpadd,
         Vpmax,
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
index 0818b6801..b7cb2636b 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
@@ -22,7 +22,7 @@ namespace Ryujinx.Tests.Cpu
 #endregion
 
 #region "ValueSource (Opcodes)"
-        private static uint[] _Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I_()
+        private static uint[] _Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_()
         {
             return new uint[]
             {
@@ -31,6 +31,7 @@ namespace Ryujinx.Tests.Cpu
                 0xf3200110u, // VBIT D0, D0, D0
                 0xf3100110u, // VBSL D0, D0, D0
                 0xf2000110u, // VAND D0, D0, D0
+                0xf2300110u, // VORN D0, D0, D0
                 0xf2200110u, // VORR D0, D0, D0
                 0xf3000110u  // VEOR D0, D0, D0
             };
@@ -51,14 +52,14 @@ namespace Ryujinx.Tests.Cpu
         private const int RndCnt = 2;
 
         [Test, Pairwise]
-        public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I([ValueSource("_Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I_")] uint opcode,
-                                                         [Range(0u, 5u)] uint rd,
-                                                         [Range(0u, 5u)] uint rn,
-                                                         [Range(0u, 5u)] uint rm,
-                                                         [Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong z,
-                                                         [Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong a,
-                                                         [Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong b,
-                                                         [Values] bool q)
+        public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I([ValueSource("_Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_")] uint opcode,
+                                                              [Range(0u, 5u)] uint rd,
+                                                              [Range(0u, 5u)] uint rn,
+                                                              [Range(0u, 5u)] uint rm,
+                                                              [Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong z,
+                                                              [Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong a,
+                                                              [Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong b,
+                                                              [Values] bool q)
         {
             if (q)
             {