mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-18 14:48:44 +02:00
CPU: Implement VFNMS.F32/64 (#1758)
* Add necessary methods / op-code * Enable Support for FMA Instruction Set * Add Intrinsics / Assembly Opcodes for VFMSUB231XX. * Add X86 Instructions for VFMSUB231XX * Implement VFNMS * Implement VFNMS Tests * Add special cases for FMA instructions. * Update PPTC Version * Remove unused Op * Move Check into Assert / Cleanup * Rename and cleanup * Whitespace * Whitespace / Rename * Re-sort * Address final requests * Implement VFMA.F64 * Simplify switch * Simplify FMA Instructions into their own IntrinsicType. * Remove whitespace * Fix indentation * Change tests for Vfnms -- disable inf / nan * Move args up, not description ;) * Undo vfma * Completely remove vfms code., * Fix order of instruction in assembler
This commit is contained in:
parent
c00d39b675
commit
b479a43939
14 changed files with 462 additions and 363 deletions
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@ -271,6 +271,10 @@ namespace ARMeilleure.CodeGen.X86
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Add(X86Instruction.Vblendvps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f3a4a, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Vblendvps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f3a4a, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Vcvtph2ps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f3813, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Vcvtph2ps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f3813, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Vcvtps2ph, new InstructionInfo(0x000f3a1d, BadOp, BadOp, BadOp, BadOp, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Vcvtps2ph, new InstructionInfo(0x000f3a1d, BadOp, BadOp, BadOp, BadOp, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Vfmsub231ps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f38ba, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Vfmsub231pd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f38ba, InstructionFlags.Vex | InstructionFlags.Prefix66 | InstructionFlags.RexW));
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Add(X86Instruction.Vfmsub231ss, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f38bb, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Vfmsub231sd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f38bb, InstructionFlags.Vex | InstructionFlags.Prefix66 | InstructionFlags.RexW));
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Add(X86Instruction.Vpblendvb, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f3a4c, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Vpblendvb, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x000f3a4c, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Xor, new InstructionInfo(0x00000031, 0x06000083, 0x06000081, BadOp, 0x00000033, InstructionFlags.None));
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Add(X86Instruction.Xor, new InstructionInfo(0x00000031, 0x06000083, 0x06000081, BadOp, 0x00000033, InstructionFlags.None));
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Add(X86Instruction.Xorpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f57, InstructionFlags.Vex | InstructionFlags.Prefix66));
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Add(X86Instruction.Xorpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f57, InstructionFlags.Vex | InstructionFlags.Prefix66));
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@ -406,12 +406,9 @@ namespace ARMeilleure.CodeGen.X86
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else
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else
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{
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{
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EnsureSameReg(dest, src1);
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EnsureSameReg(dest, src1);
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Debug.Assert(src3.GetRegister().Index == 0);
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Debug.Assert(src3.GetRegister().Index == 0);
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context.Assembler.WriteInstruction(info.Inst, dest, src1, src2);
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context.Assembler.WriteInstruction(info.Inst, dest, src1, src2);
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}
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}
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break;
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break;
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}
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}
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@ -435,6 +432,23 @@ namespace ARMeilleure.CodeGen.X86
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break;
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break;
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}
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}
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case IntrinsicType.Fma:
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{
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Operand dest = operation.Destination;
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Operand src1 = operation.GetSource(0);
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Operand src2 = operation.GetSource(1);
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Operand src3 = operation.GetSource(2);
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EnsureSameType(dest, src1, src2, src3);
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EnsureSameReg(dest, src1);
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Debug.Assert(!dest.Type.IsInteger());
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Debug.Assert(HardwareCapabilities.SupportsVexEncoding);
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context.Assembler.WriteInstruction(info.Inst, dest, src2, src3);
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break;
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}
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}
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}
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}
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}
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else
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else
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@ -164,6 +164,10 @@ namespace ARMeilleure.CodeGen.X86
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Add(Intrinsic.X86Unpcklps, new IntrinsicInfo(X86Instruction.Unpcklps, IntrinsicType.Binary));
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Add(Intrinsic.X86Unpcklps, new IntrinsicInfo(X86Instruction.Unpcklps, IntrinsicType.Binary));
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Add(Intrinsic.X86Vcvtph2ps, new IntrinsicInfo(X86Instruction.Vcvtph2ps, IntrinsicType.Unary));
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Add(Intrinsic.X86Vcvtph2ps, new IntrinsicInfo(X86Instruction.Vcvtph2ps, IntrinsicType.Unary));
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Add(Intrinsic.X86Vcvtps2ph, new IntrinsicInfo(X86Instruction.Vcvtps2ph, IntrinsicType.BinaryImm));
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Add(Intrinsic.X86Vcvtps2ph, new IntrinsicInfo(X86Instruction.Vcvtps2ph, IntrinsicType.BinaryImm));
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Add(Intrinsic.X86Vfmsub231pd, new IntrinsicInfo(X86Instruction.Vfmsub231pd, IntrinsicType.Fma));
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Add(Intrinsic.X86Vfmsub231ps, new IntrinsicInfo(X86Instruction.Vfmsub231ps, IntrinsicType.Fma));
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Add(Intrinsic.X86Vfmsub231sd, new IntrinsicInfo(X86Instruction.Vfmsub231sd, IntrinsicType.Fma));
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Add(Intrinsic.X86Vfmsub231ss, new IntrinsicInfo(X86Instruction.Vfmsub231ss, IntrinsicType.Fma));
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Add(Intrinsic.X86Xorpd, new IntrinsicInfo(X86Instruction.Xorpd, IntrinsicType.Binary));
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Add(Intrinsic.X86Xorpd, new IntrinsicInfo(X86Instruction.Xorpd, IntrinsicType.Binary));
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Add(Intrinsic.X86Xorps, new IntrinsicInfo(X86Instruction.Xorps, IntrinsicType.Binary));
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Add(Intrinsic.X86Xorps, new IntrinsicInfo(X86Instruction.Xorps, IntrinsicType.Binary));
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}
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}
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@ -11,6 +11,7 @@ namespace ARMeilleure.CodeGen.X86
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BinaryImm,
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BinaryImm,
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Crc32,
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Crc32,
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Ternary,
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Ternary,
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TernaryImm
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TernaryImm,
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Fma
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}
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}
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}
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}
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@ -1309,7 +1309,7 @@ namespace ARMeilleure.CodeGen.X86
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IntrinsicOperation intrinOp = (IntrinsicOperation)operation;
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IntrinsicOperation intrinOp = (IntrinsicOperation)operation;
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IntrinsicInfo info = IntrinsicTable.GetInfo(intrinOp.Intrinsic);
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IntrinsicInfo info = IntrinsicTable.GetInfo(intrinOp.Intrinsic);
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return info.Type == IntrinsicType.Crc32 || IsVexSameOperandDestSrc1(operation);
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return info.Type == IntrinsicType.Crc32 || info.Type == IntrinsicType.Fma || IsVexSameOperandDestSrc1(operation);
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}
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}
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private static bool IsVexSameOperandDestSrc1(Operation operation)
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private static bool IsVexSameOperandDestSrc1(Operation operation)
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@ -200,6 +200,10 @@ namespace ARMeilleure.CodeGen.X86
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Vblendvps,
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Vblendvps,
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Vcvtph2ps,
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Vcvtph2ps,
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Vcvtps2ph,
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Vcvtps2ph,
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Vfmsub231ps,
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Vfmsub231pd,
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Vfmsub231ss,
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Vfmsub231sd,
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Vpblendvb,
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Vpblendvb,
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Xor,
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Xor,
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Xorpd,
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Xorpd,
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@ -821,6 +821,7 @@ namespace ARMeilleure.Decoders
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SetA32("111100101x11xxxxxxxxxxxxxxx0xxxx", InstName.Vext, InstEmit32.Vext, OpCode32SimdExt.Create);
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SetA32("111100101x11xxxxxxxxxxxxxxx0xxxx", InstName.Vext, InstEmit32.Vext, OpCode32SimdExt.Create);
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SetA32("<<<<11101x10xxxxxxxx101xx0x0xxxx", InstName.Vfma, InstEmit32.Vfma_S, OpCode32SimdRegS.Create);
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SetA32("<<<<11101x10xxxxxxxx101xx0x0xxxx", InstName.Vfma, InstEmit32.Vfma_S, OpCode32SimdRegS.Create);
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SetA32("<<<<11101x10xxxxxxxx101xx1x0xxxx", InstName.Vfms, InstEmit32.Vfms_S, OpCode32SimdRegS.Create);
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SetA32("<<<<11101x10xxxxxxxx101xx1x0xxxx", InstName.Vfms, InstEmit32.Vfms_S, OpCode32SimdRegS.Create);
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SetA32("<<<<11101x01xxxxxxxx101xx0x0xxxx", InstName.Vfnms, InstEmit32.Vfnms_S, OpCode32SimdRegS.Create);
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SetA32("1111001x0x<<xxxxxxxx0000xxx0xxxx", InstName.Vhadd, InstEmit32.Vhadd, OpCode32SimdReg.Create);
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SetA32("1111001x0x<<xxxxxxxx0000xxx0xxxx", InstName.Vhadd, InstEmit32.Vhadd, OpCode32SimdReg.Create);
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SetA32("111101001x10xxxxxxxxxx00xxxxxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemSingle.Create);
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SetA32("111101001x10xxxxxxxxxx00xxxxxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemSingle.Create);
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SetA32("111101000x10xxxxxxxx0111xxxxxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemPair.Create); // Regs = 1.
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SetA32("111101000x10xxxxxxxx0111xxxxxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemPair.Create); // Regs = 1.
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@ -284,6 +284,21 @@ namespace ARMeilleure.Instructions
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}
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}
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}
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}
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public static void Vfnms_S(ArmEmitterContext context) // Fused.
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{
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if (Optimizations.FastFP && Optimizations.UseFma)
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{
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EmitScalarTernaryOpF32(context, Intrinsic.X86Vfmsub231ss, Intrinsic.X86Vfmsub231sd);
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}
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else
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{
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EmitScalarTernaryOpF32(context, (op1, op2, op3) =>
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{
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return EmitSoftFloatCall(context, nameof(SoftFloat32.FPMulAdd), context.Negate(op1), op2, op3);
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});
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}
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}
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public static void Vhadd(ArmEmitterContext context)
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public static void Vhadd(ArmEmitterContext context)
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{
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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@ -901,6 +901,20 @@ namespace ARMeilleure.Instructions
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context.Copy(initialD, res);
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context.Copy(initialD, res);
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}
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}
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public static void EmitScalarTernaryOpF32(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
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{
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OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
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bool doubleSize = (op.Size & 1) != 0;
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Intrinsic inst = doubleSize ? inst64 : inst32;
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EmitScalarTernaryOpSimd32(context, (d, n, m) =>
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{
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return context.AddIntrinsic(inst, d, n, m);
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});
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}
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public static void EmitScalarTernaryOpF32(ArmEmitterContext context, Intrinsic inst32pt1, Intrinsic inst64pt1, Intrinsic inst32pt2, Intrinsic inst64pt2)
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public static void EmitScalarTernaryOpF32(ArmEmitterContext context, Intrinsic inst32pt1, Intrinsic inst64pt1, Intrinsic inst32pt2, Intrinsic inst64pt2)
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{
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{
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OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
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OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
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@ -571,6 +571,7 @@ namespace ARMeilleure.Instructions
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Vext,
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Vext,
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Vfma,
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Vfma,
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Vfms,
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Vfms,
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Vfnms,
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Vhadd,
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Vhadd,
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Vld1,
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Vld1,
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Vld2,
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Vld2,
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@ -153,6 +153,10 @@ namespace ARMeilleure.IntermediateRepresentation
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X86Unpcklps,
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X86Unpcklps,
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X86Vcvtph2ps,
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X86Vcvtph2ps,
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X86Vcvtps2ph,
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X86Vcvtps2ph,
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X86Vfmsub231pd,
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X86Vfmsub231ps,
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X86Vfmsub231sd,
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X86Vfmsub231ss,
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X86Xorpd,
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X86Xorpd,
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X86Xorps
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X86Xorps
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}
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}
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@ -15,6 +15,7 @@ namespace ARMeilleure
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public static bool UsePopCntIfAvailable { get; set; } = true;
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public static bool UsePopCntIfAvailable { get; set; } = true;
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public static bool UseAvxIfAvailable { get; set; } = true;
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public static bool UseAvxIfAvailable { get; set; } = true;
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public static bool UseF16cIfAvailable { get; set; } = true;
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public static bool UseF16cIfAvailable { get; set; } = true;
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public static bool UseFmaIfAvailable { get; set; } = true;
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public static bool UseAesniIfAvailable { get; set; } = true;
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public static bool UseAesniIfAvailable { get; set; } = true;
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public static bool UsePclmulqdqIfAvailable { get; set; } = true;
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public static bool UsePclmulqdqIfAvailable { get; set; } = true;
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@ -33,6 +34,7 @@ namespace ARMeilleure
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internal static bool UsePopCnt => UsePopCntIfAvailable && HardwareCapabilities.SupportsPopcnt;
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internal static bool UsePopCnt => UsePopCntIfAvailable && HardwareCapabilities.SupportsPopcnt;
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internal static bool UseAvx => UseAvxIfAvailable && HardwareCapabilities.SupportsAvx && !ForceLegacySse;
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internal static bool UseAvx => UseAvxIfAvailable && HardwareCapabilities.SupportsAvx && !ForceLegacySse;
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internal static bool UseF16c => UseF16cIfAvailable && HardwareCapabilities.SupportsF16c;
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internal static bool UseF16c => UseF16cIfAvailable && HardwareCapabilities.SupportsF16c;
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internal static bool UseFma => UseFmaIfAvailable && HardwareCapabilities.SupportsFma;
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internal static bool UseAesni => UseAesniIfAvailable && HardwareCapabilities.SupportsAesni;
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internal static bool UseAesni => UseAesniIfAvailable && HardwareCapabilities.SupportsAesni;
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internal static bool UsePclmulqdq => UsePclmulqdqIfAvailable && HardwareCapabilities.SupportsPclmulqdq;
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internal static bool UsePclmulqdq => UsePclmulqdqIfAvailable && HardwareCapabilities.SupportsPclmulqdq;
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}
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}
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@ -21,7 +21,7 @@ namespace ARMeilleure.Translation.PTC
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{
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{
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private const string HeaderMagic = "PTChd";
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private const string HeaderMagic = "PTChd";
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private const int InternalVersion = 1650; //! To be incremented manually for each change to the ARMeilleure project.
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private const int InternalVersion = 1758; //! To be incremented manually for each change to the ARMeilleure project.
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private const string ActualDir = "0";
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private const string ActualDir = "0";
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private const string BackupDir = "1";
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private const string BackupDir = "1";
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@ -184,8 +184,8 @@ namespace Ryujinx.Tests.Cpu
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private const int RndCnt = 2;
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private const int RndCnt = 2;
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private static readonly bool NoZeros = false;
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private static readonly bool NoZeros = false;
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private static readonly bool NoInfs = false;
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private static readonly bool NoInfs = true;
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private static readonly bool NoNaNs = false;
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private static readonly bool NoNaNs = true;
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[Explicit]
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[Explicit]
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[Test, Pairwise, Description("VADD.f32 V0, V0, V0")]
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[Test, Pairwise, Description("VADD.f32 V0, V0, V0")]
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@ -293,6 +293,41 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn(fpsrMask: Fpsr.Nzcv);
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CompareAgainstUnicorn(fpsrMask: Fpsr.Nzcv);
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}
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}
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[Test, Pairwise, Description("VFNMS.F<size> <Vd>, <Vn>, <Vm>")]
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public void Vfnms([Values(0u, 1u)] uint rd,
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[Values(0u, 1u)] uint rn,
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[Values(0u, 1u)] uint rm,
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[Values(2u, 3u)] uint size,
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[ValueSource("_2S_F_")] ulong z,
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[ValueSource("_2S_F_")] ulong a,
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[ValueSource("_2S_F_")] ulong b)
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{
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uint opcode = 0xee900a00;
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if (size == 2)
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{
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opcode |= (((rm & 0x1) << 5) | (rm & 0x1e) >> 1);
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opcode |= (((rd & 0x1) << 22) | (rd & 0x1e) << 11);
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opcode |= (((rn & 0x1) << 7) | (rn & 0x1e) >> 15);
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}
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else
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{
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opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0);
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opcode |= (((rd & 0x10) << 18) | (rd & 0xf) << 12);
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opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16);
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}
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opcode |= ((size & 3) << 8);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VMLSL.<type><size> <Vd>, <Vn>, <Vm>")]
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[Test, Pairwise, Description("VMLSL.<type><size> <Vd>, <Vn>, <Vm>")]
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public void Vmlsl_I([Values(0u)] uint rd,
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public void Vmlsl_I([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(1u, 0u)] uint rn,
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