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Fix FRSQRTS and FCM* (scalar) instructions

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This commit is contained in:
gdkchan 2018-04-06 10:20:17 -03:00
parent a7ecf6dd2d
commit df3cbadceb
2 changed files with 53 additions and 20 deletions
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41
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
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@ -512,21 +512,33 @@ namespace ChocolArm64.Instruction
public static void Frsqrts_S(AILEmitterCtx Context)
{
EmitScalarBinaryOpF(Context, () => EmitFrsqrts(Context));
EmitFrsqrts(Context, 0, Scalar: true);
}
public static void Frsqrts_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpF(Context, () => EmitFrsqrts(Context));
}
private static void EmitFrsqrts(AILEmitterCtx Context)
{
IAOpCodeSimd Op = (IAOpCodeSimd)Context.CurrOp;
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
int SizeF = Op.Size & 1;
Context.Emit(OpCodes.Mul);
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
for (int Index = 0; Index < Bytes >> SizeF + 2; Index++)
{
EmitFrsqrts(Context, Index, Scalar: false);
}
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
private static void EmitFrsqrts(AILEmitterCtx Context, int Index, bool Scalar)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
int SizeF = Op.Size & 1;
if (SizeF == 0)
{
@ -537,7 +549,11 @@ namespace ChocolArm64.Instruction
Context.EmitLdc_R8(3);
}
Context.Emit(OpCodes.Add);
EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
EmitVectorExtractF(Context, Op.Rm, Index, SizeF);
Context.Emit(OpCodes.Mul);
Context.Emit(OpCodes.Sub);
if (SizeF == 0)
{
@ -549,6 +565,13 @@ namespace ChocolArm64.Instruction
}
Context.Emit(OpCodes.Mul);
if (Scalar)
{
EmitVectorZeroAll(Context, Op.Rd);
}
EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
}
public static void Fsqrt_S(AILEmitterCtx Context)

28
ChocolArm64/Instruction/AInstEmitSimdCmp.cs
View file

@ -313,13 +313,7 @@ namespace ChocolArm64.Instruction
private static void EmitScalarFcmp(AILEmitterCtx Context, OpCode ILOp)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
int SizeF = Op.Size & 1;
EmitFcmp(Context, ILOp, 0);
EmitScalarSetF(Context, Op.Rd, SizeF);
EmitFcmp(Context, ILOp, 0, Scalar: true);
}
private static void EmitVectorFcmp(AILEmitterCtx Context, OpCode ILOp)
@ -332,7 +326,7 @@ namespace ChocolArm64.Instruction
for (int Index = 0; Index < Bytes >> SizeF + 2; Index++)
{
EmitFcmp(Context, ILOp, Index);
EmitFcmp(Context, ILOp, Index, Scalar: false);
}
if (Op.RegisterSize == ARegisterSize.SIMD64)
@ -341,7 +335,7 @@ namespace ChocolArm64.Instruction
}
}
private static void EmitFcmp(AILEmitterCtx Context, OpCode ILOp, int Index)
private static void EmitFcmp(AILEmitterCtx Context, OpCode ILOp, int Index, bool Scalar)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
@ -369,13 +363,29 @@ namespace ChocolArm64.Instruction
Context.Emit(ILOp, LblTrue);
if (Scalar)
{
EmitVectorZeroAll(Context, Op.Rd);
}
else
{
EmitVectorInsert(Context, Op.Rd, Index, SizeF + 2, 0);
}
Context.Emit(OpCodes.Br_S, LblEnd);
Context.MarkLabel(LblTrue);
if (Scalar)
{
EmitVectorInsert(Context, Op.Rd, Index, 3, (long)SzMask);
EmitVectorZeroUpper(Context, Op.Rd);
}
else
{
EmitVectorInsert(Context, Op.Rd, Index, SizeF + 2, (long)SzMask);
}
Context.MarkLabel(LblEnd);
}