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CPU - Implement FCVTMS (Vector) (#2937)
* Add FCVTMS_V Implementation to Armeilleure * Fix opcode designation * Add tests * Amend Ptc version * Fix OpCode / Tests * Create Math.Floor helper method + Update implementation * Address gdk comments * Re-address gdk comments * Update ARMeilleure/Decoders/OpCodeTable.cs Co-authored-by: gdkchan <gab.dark.100@gmail.com> * Update Tests to use 2S (4S) and 2D Co-authored-by: gdkchan <gab.dark.100@gmail.com>
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5 changed files with 17 additions and 1 deletions
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@ -285,6 +285,7 @@ namespace ARMeilleure.Decoders
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SetA64("0>1011100<100001110010xxxxxxxxxx", InstName.Fcvtau_V, InstEmit.Fcvtau_V, OpCodeSimd.Create);
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SetA64("0>1011100<100001110010xxxxxxxxxx", InstName.Fcvtau_V, InstEmit.Fcvtau_V, OpCodeSimd.Create);
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SetA64("0x0011100x100001011110xxxxxxxxxx", InstName.Fcvtl_V, InstEmit.Fcvtl_V, OpCodeSimd.Create);
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SetA64("0x0011100x100001011110xxxxxxxxxx", InstName.Fcvtl_V, InstEmit.Fcvtl_V, OpCodeSimd.Create);
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SetA64("x00111100x110000000000xxxxxxxxxx", InstName.Fcvtms_Gp, InstEmit.Fcvtms_Gp, OpCodeSimdCvt.Create);
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SetA64("x00111100x110000000000xxxxxxxxxx", InstName.Fcvtms_Gp, InstEmit.Fcvtms_Gp, OpCodeSimdCvt.Create);
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SetA64("0>0011100<100001101110xxxxxxxxxx", InstName.Fcvtms_V, InstEmit.Fcvtms_V, OpCodeSimd.Create);
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SetA64("x00111100x110001000000xxxxxxxxxx", InstName.Fcvtmu_Gp, InstEmit.Fcvtmu_Gp, OpCodeSimdCvt.Create);
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SetA64("x00111100x110001000000xxxxxxxxxx", InstName.Fcvtmu_Gp, InstEmit.Fcvtmu_Gp, OpCodeSimdCvt.Create);
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SetA64("0x0011100x100001011010xxxxxxxxxx", InstName.Fcvtn_V, InstEmit.Fcvtn_V, OpCodeSimd.Create);
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SetA64("0x0011100x100001011010xxxxxxxxxx", InstName.Fcvtn_V, InstEmit.Fcvtn_V, OpCodeSimd.Create);
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SetA64("010111100x100001101010xxxxxxxxxx", InstName.Fcvtns_S, InstEmit.Fcvtns_S, OpCodeSimd.Create);
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SetA64("010111100x100001101010xxxxxxxxxx", InstName.Fcvtns_S, InstEmit.Fcvtns_S, OpCodeSimd.Create);
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@ -217,6 +217,18 @@ namespace ARMeilleure.Instructions
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}
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}
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}
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}
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public static void Fcvtms_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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{
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EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsMinusInfinity, scalar: false);
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}
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else
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{
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EmitFcvt(context, (op1) => EmitUnaryMathCall(context, nameof(Math.Floor), op1), signed: true, scalar: false);
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}
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}
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public static void Fcvtmu_Gp(ArmEmitterContext context)
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public static void Fcvtmu_Gp(ArmEmitterContext context)
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{
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseSse41)
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@ -188,6 +188,7 @@ namespace ARMeilleure.Instructions
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Fcvtau_V,
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Fcvtau_V,
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Fcvtl_V,
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Fcvtl_V,
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Fcvtms_Gp,
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Fcvtms_Gp,
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Fcvtms_V,
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Fcvtmu_Gp,
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Fcvtmu_Gp,
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Fcvtn_V,
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Fcvtn_V,
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Fcvtns_S,
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Fcvtns_S,
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@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
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private const string OuterHeaderMagicString = "PTCohd\0\0";
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private const string OuterHeaderMagicString = "PTCohd\0\0";
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private const string InnerHeaderMagicString = "PTCihd\0\0";
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private const string InnerHeaderMagicString = "PTCihd\0\0";
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private const uint InternalVersion = 2908; //! To be incremented manually for each change to the ARMeilleure project.
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private const uint InternalVersion = 2937; //! To be incremented manually for each change to the ARMeilleure project.
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private const string ActualDir = "0";
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private const string ActualDir = "0";
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private const string BackupDir = "1";
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private const string BackupDir = "1";
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@ -865,6 +865,7 @@ namespace Ryujinx.Tests.Cpu
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{
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{
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0x0E21C800u, // FCVTAS V0.2S, V0.2S
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0x0E21C800u, // FCVTAS V0.2S, V0.2S
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0x2E21C800u, // FCVTAU V0.2S, V0.2S
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0x2E21C800u, // FCVTAU V0.2S, V0.2S
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0x0E21B800u, // FCVTMS V0.2S, V0.2S
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0x0E21A800u, // FCVTNS V0.2S, V0.2S
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0x0E21A800u, // FCVTNS V0.2S, V0.2S
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0x2E21A800u, // FCVTNU V0.2S, V0.2S
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0x2E21A800u, // FCVTNU V0.2S, V0.2S
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0x0EA1B800u, // FCVTZS V0.2S, V0.2S
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0x0EA1B800u, // FCVTZS V0.2S, V0.2S
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@ -878,6 +879,7 @@ namespace Ryujinx.Tests.Cpu
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{
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{
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0x4E61C800u, // FCVTAS V0.2D, V0.2D
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0x4E61C800u, // FCVTAS V0.2D, V0.2D
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0x6E61C800u, // FCVTAU V0.2D, V0.2D
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0x6E61C800u, // FCVTAU V0.2D, V0.2D
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0x4E61B800u, // FCVTMS V0.2D, V0.2D
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0x4E61A800u, // FCVTNS V0.2D, V0.2D
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0x4E61A800u, // FCVTNS V0.2D, V0.2D
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0x6E61A800u, // FCVTNU V0.2D, V0.2D
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0x6E61A800u, // FCVTNU V0.2D, V0.2D
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0x4EE1B800u, // FCVTZS V0.2D, V0.2D
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0x4EE1B800u, // FCVTZS V0.2D, V0.2D
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