From eba682b767a60db51ff624ae48a3ca0124634705 Mon Sep 17 00:00:00 2001 From: gdkchan Date: Thu, 25 Aug 2022 06:59:34 -0300 Subject: [PATCH] Implement some 32-bit Thumb instructions (#3614) * Implement some 32-bit Thumb instructions * Optimize OpCode32MemMult using PopCount --- ARMeilleure/Decoders/IOpCode32MemRsImm.cs | 8 +++ ARMeilleure/Decoders/OpCode32MemMult.cs | 11 ++-- ARMeilleure/Decoders/OpCode32MemRsImm.cs | 2 +- ARMeilleure/Decoders/OpCodeT16BImmCmp.cs | 4 +- ARMeilleure/Decoders/OpCodeT32MemImm8D.cs | 31 +++++++++++ ARMeilleure/Decoders/OpCodeT32MemLdEx.cs | 24 +++++++++ ARMeilleure/Decoders/OpCodeT32MemMult.cs | 52 +++++++++++++++++++ ARMeilleure/Decoders/OpCodeT32MemRsImm.cs | 30 +++++++++++ ARMeilleure/Decoders/OpCodeT32MemStEx.cs | 25 +++++++++ ARMeilleure/Decoders/OpCodeTable.cs | 10 ++++ ARMeilleure/Instructions/InstEmitFlow32.cs | 2 +- .../Instructions/InstEmitMemoryHelper.cs | 4 +- ARMeilleure/Translation/ControlFlowGraph.cs | 2 +- 13 files changed, 190 insertions(+), 15 deletions(-) create mode 100644 ARMeilleure/Decoders/IOpCode32MemRsImm.cs create mode 100644 ARMeilleure/Decoders/OpCodeT32MemImm8D.cs create mode 100644 ARMeilleure/Decoders/OpCodeT32MemLdEx.cs create mode 100644 ARMeilleure/Decoders/OpCodeT32MemMult.cs create mode 100644 ARMeilleure/Decoders/OpCodeT32MemRsImm.cs create mode 100644 ARMeilleure/Decoders/OpCodeT32MemStEx.cs diff --git a/ARMeilleure/Decoders/IOpCode32MemRsImm.cs b/ARMeilleure/Decoders/IOpCode32MemRsImm.cs new file mode 100644 index 000000000..65b7ee0b4 --- /dev/null +++ b/ARMeilleure/Decoders/IOpCode32MemRsImm.cs @@ -0,0 +1,8 @@ +namespace ARMeilleure.Decoders +{ + interface IOpCode32MemRsImm : IOpCode32Mem + { + int Rm { get; } + ShiftType ShiftType { get; } + } +} \ No newline at end of file diff --git a/ARMeilleure/Decoders/OpCode32MemMult.cs b/ARMeilleure/Decoders/OpCode32MemMult.cs index cc726196d..522b96bb9 100644 --- a/ARMeilleure/Decoders/OpCode32MemMult.cs +++ b/ARMeilleure/Decoders/OpCode32MemMult.cs @@ -1,3 +1,5 @@ +using System.Numerics; + namespace ARMeilleure.Decoders { class OpCode32MemMult : OpCode32, IOpCode32MemMult @@ -23,14 +25,7 @@ namespace ARMeilleure.Decoders RegisterMask = opCode & 0xffff; - int regsSize = 0; - - for (int index = 0; index < 16; index++) - { - regsSize += (RegisterMask >> index) & 1; - } - - regsSize *= 4; + int regsSize = BitOperations.PopCount((uint)RegisterMask) * 4; if (!u) { diff --git a/ARMeilleure/Decoders/OpCode32MemRsImm.cs b/ARMeilleure/Decoders/OpCode32MemRsImm.cs index dc5f0fd35..e1284cf7e 100644 --- a/ARMeilleure/Decoders/OpCode32MemRsImm.cs +++ b/ARMeilleure/Decoders/OpCode32MemRsImm.cs @@ -1,6 +1,6 @@ namespace ARMeilleure.Decoders { - class OpCode32MemRsImm : OpCode32Mem + class OpCode32MemRsImm : OpCode32Mem, IOpCode32MemRsImm { public int Rm { get; } public ShiftType ShiftType { get; } diff --git a/ARMeilleure/Decoders/OpCodeT16BImmCmp.cs b/ARMeilleure/Decoders/OpCodeT16BImmCmp.cs index ab7ae13f7..68ebac75c 100644 --- a/ARMeilleure/Decoders/OpCodeT16BImmCmp.cs +++ b/ARMeilleure/Decoders/OpCodeT16BImmCmp.cs @@ -1,10 +1,10 @@ namespace ARMeilleure.Decoders { - class OpCodeT16BImmCmp : OpCodeT16 + class OpCodeT16BImmCmp : OpCodeT16, IOpCode32BImm { public int Rn { get; } - public int Immediate { get; } + public long Immediate { get; } public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16BImmCmp(inst, address, opCode); diff --git a/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs b/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs new file mode 100644 index 000000000..18eeffa43 --- /dev/null +++ b/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs @@ -0,0 +1,31 @@ +namespace ARMeilleure.Decoders +{ + class OpCodeT32MemImm8D : OpCodeT32, IOpCode32Mem + { + public int Rt { get; } + public int Rt2 { get; } + public int Rn { get; } + public bool WBack { get; } + public bool IsLoad { get; } + public bool Index { get; } + public bool Add { get; } + public int Immediate { get; } + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MemImm8D(inst, address, opCode); + + public OpCodeT32MemImm8D(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Rt2 = (opCode >> 8) & 0xf; + Rt = (opCode >> 12) & 0xf; + Rn = (opCode >> 16) & 0xf; + + Index = ((opCode >> 24) & 1) != 0; + Add = ((opCode >> 23) & 1) != 0; + WBack = ((opCode >> 21) & 1) != 0; + + Immediate = opCode & 0xff; + + IsLoad = ((opCode >> 20) & 1) != 0; + } + } +} \ No newline at end of file diff --git a/ARMeilleure/Decoders/OpCodeT32MemLdEx.cs b/ARMeilleure/Decoders/OpCodeT32MemLdEx.cs new file mode 100644 index 000000000..da565f61d --- /dev/null +++ b/ARMeilleure/Decoders/OpCodeT32MemLdEx.cs @@ -0,0 +1,24 @@ +namespace ARMeilleure.Decoders +{ + class OpCodeT32MemLdEx : OpCodeT32, IOpCode32MemEx + { + public int Rd => 0; + public int Rt { get; } + public int Rn { get; } + + public bool WBack => false; + public bool IsLoad => true; + public bool Index => false; + public bool Add => false; + + public int Immediate => 0; + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MemLdEx(inst, address, opCode); + + public OpCodeT32MemLdEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Rt = (opCode >> 12) & 0xf; + Rn = (opCode >> 16) & 0xf; + } + } +} diff --git a/ARMeilleure/Decoders/OpCodeT32MemMult.cs b/ARMeilleure/Decoders/OpCodeT32MemMult.cs new file mode 100644 index 000000000..a9ba306dc --- /dev/null +++ b/ARMeilleure/Decoders/OpCodeT32MemMult.cs @@ -0,0 +1,52 @@ +using System.Numerics; + +namespace ARMeilleure.Decoders +{ + class OpCodeT32MemMult : OpCodeT32, IOpCode32MemMult + { + public int Rn { get; } + + public int RegisterMask { get; } + public int Offset { get; } + public int PostOffset { get; } + + public bool IsLoad { get; } + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MemMult(inst, address, opCode); + + public OpCodeT32MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Rn = (opCode >> 16) & 0xf; + + bool isLoad = (opCode & (1 << 20)) != 0; + bool w = (opCode & (1 << 21)) != 0; + bool u = (opCode & (1 << 23)) != 0; + bool p = (opCode & (1 << 24)) != 0; + + RegisterMask = opCode & 0xffff; + + int regsSize = BitOperations.PopCount((uint)RegisterMask) * 4; + + if (!u) + { + Offset -= regsSize; + } + + if (u == p) + { + Offset += 4; + } + + if (w) + { + PostOffset = u ? regsSize : -regsSize; + } + else + { + PostOffset = 0; + } + + IsLoad = isLoad; + } + } +} \ No newline at end of file diff --git a/ARMeilleure/Decoders/OpCodeT32MemRsImm.cs b/ARMeilleure/Decoders/OpCodeT32MemRsImm.cs new file mode 100644 index 000000000..056d3b465 --- /dev/null +++ b/ARMeilleure/Decoders/OpCodeT32MemRsImm.cs @@ -0,0 +1,30 @@ +namespace ARMeilleure.Decoders +{ + class OpCodeT32MemRsImm : OpCodeT32, IOpCode32MemRsImm + { + public int Rt { get; } + public int Rn { get; } + public int Rm { get; } + public ShiftType ShiftType => ShiftType.Lsl; + + public bool WBack => false; + public bool IsLoad { get; } + public bool Index => true; + public bool Add => true; + + public int Immediate { get; } + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MemRsImm(inst, address, opCode); + + public OpCodeT32MemRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Rm = (opCode >> 0) & 0xf; + Rt = (opCode >> 12) & 0xf; + Rn = (opCode >> 16) & 0xf; + + IsLoad = (opCode & (1 << 20)) != 0; + + Immediate = (opCode >> 4) & 3; + } + } +} diff --git a/ARMeilleure/Decoders/OpCodeT32MemStEx.cs b/ARMeilleure/Decoders/OpCodeT32MemStEx.cs new file mode 100644 index 000000000..8fe1950ed --- /dev/null +++ b/ARMeilleure/Decoders/OpCodeT32MemStEx.cs @@ -0,0 +1,25 @@ +namespace ARMeilleure.Decoders +{ + class OpCodeT32MemStEx : OpCodeT32, IOpCode32MemEx + { + public int Rd { get; } + public int Rt { get; } + public int Rn { get; } + + public bool WBack => false; + public bool IsLoad => false; + public bool Index => false; + public bool Add => false; + + public int Immediate => 0; + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MemStEx(inst, address, opCode); + + public OpCodeT32MemStEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Rd = (opCode >> 0) & 0xf; + Rt = (opCode >> 12) & 0xf; + Rn = (opCode >> 16) & 0xf; + } + } +} diff --git a/ARMeilleure/Decoders/OpCodeTable.cs b/ARMeilleure/Decoders/OpCodeTable.cs index 023b9a4a9..7fee8a719 100644 --- a/ARMeilleure/Decoders/OpCodeTable.cs +++ b/ARMeilleure/Decoders/OpCodeTable.cs @@ -1070,14 +1070,19 @@ namespace ARMeilleure.Decoders SetT32("11110x011011xxxx0xxx1111xxxxxxxx", InstName.Cmp, InstEmit32.Cmp, OpCodeT32AluImm.Create); SetT32("11101010100x1>1<<<xxxxxxxx", InstName.Str, InstEmit32.Str, OpCodeT32MemImm8.Create); SetT32("111110001100xxxxxxxxxxxxxxxxxxxx", InstName.Str, InstEmit32.Str, OpCodeT32MemImm12.Create); + SetT32("111110000100<<<xxxxxxxx", InstName.Strb, InstEmit32.Strb, OpCodeT32MemImm8.Create); SetT32("111110001000xxxxxxxxxxxxxxxxxxxx", InstName.Strb, InstEmit32.Strb, OpCodeT32MemImm12.Create); + SetT32("1110100>x1>0<<<xxxxxxxx", InstName.Strh, InstEmit32.Strh, OpCodeT32MemImm8.Create); SetT32("111110001010xxxxxxxxxxxxxxxxxxxx", InstName.Strh, InstEmit32.Strh, OpCodeT32MemImm12.Create); SetT32("11101011101 Blocks { get; } public BasicBlock[] PostOrderBlocks => _postOrderBlocks; - public int[] PostOrderMap => _postOrderMap; + public int[] PostOrderMap => _postOrderMap; public ControlFlowGraph(BasicBlock entry, IntrusiveList blocks, int localsCount) {