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Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)
* Add host CPU memory barriers for DMB/DSB and ordered load/store * PPTC version bump * Revert to old barrier order
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7e967d796c
commit
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6 changed files with 21 additions and 5 deletions
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@ -358,6 +358,12 @@ namespace ARMeilleure.CodeGen.X86
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WriteInstruction(dest, source, type, X86Instruction.Lea);
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WriteInstruction(dest, source, type, X86Instruction.Lea);
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}
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}
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public void LockOr(Operand dest, Operand source, OperandType type)
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{
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WriteByte(LockPrefix);
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WriteInstruction(dest, source, type, X86Instruction.Or);
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}
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public void Mov(Operand dest, Operand source, OperandType type)
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public void Mov(Operand dest, Operand source, OperandType type)
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{
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{
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WriteInstruction(dest, source, type, X86Instruction.Mov);
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WriteInstruction(dest, source, type, X86Instruction.Mov);
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@ -49,6 +49,7 @@ namespace ARMeilleure.CodeGen.X86
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Add(Instruction.Load, GenerateLoad);
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Add(Instruction.Load, GenerateLoad);
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Add(Instruction.Load16, GenerateLoad16);
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Add(Instruction.Load16, GenerateLoad16);
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Add(Instruction.Load8, GenerateLoad8);
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Add(Instruction.Load8, GenerateLoad8);
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Add(Instruction.MemoryBarrier, GenerateMemoryBarrier);
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Add(Instruction.Multiply, GenerateMultiply);
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Add(Instruction.Multiply, GenerateMultiply);
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Add(Instruction.Multiply64HighSI, GenerateMultiply64HighSI);
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Add(Instruction.Multiply64HighSI, GenerateMultiply64HighSI);
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Add(Instruction.Multiply64HighUI, GenerateMultiply64HighUI);
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Add(Instruction.Multiply64HighUI, GenerateMultiply64HighUI);
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@ -976,6 +977,11 @@ namespace ARMeilleure.CodeGen.X86
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context.Assembler.Movzx8(value, address, value.Type);
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context.Assembler.Movzx8(value, address, value.Type);
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}
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}
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private static void GenerateMemoryBarrier(CodeGenContext context, Operation operation)
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{
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context.Assembler.LockOr(MemoryOp(OperandType.I64, Register(X86Register.Rsp)), Const(0), OperandType.I32);
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}
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private static void GenerateMultiply(CodeGenContext context, Operation operation)
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private static void GenerateMultiply(CodeGenContext context, Operation operation)
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{
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{
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Operand dest = operation.Destination;
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Operand dest = operation.Destination;
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@ -167,9 +167,7 @@ namespace ARMeilleure.Instructions
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private static void EmitBarrier(ArmEmitterContext context)
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private static void EmitBarrier(ArmEmitterContext context)
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{
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{
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// Note: This barrier is most likely not necessary, and probably
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context.MemoryBarrier();
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// doesn't make any difference since we need to do a ton of stuff
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// (software MMU emulation) to read or write anything anyway.
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}
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}
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}
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}
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}
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}
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@ -26,6 +26,7 @@ namespace ARMeilleure.IntermediateRepresentation
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Load16,
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Load16,
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Load8,
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Load8,
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LoadArgument,
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LoadArgument,
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MemoryBarrier,
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Multiply,
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Multiply,
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Multiply64HighSI,
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Multiply64HighSI,
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Multiply64HighUI,
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Multiply64HighUI,
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@ -325,6 +325,11 @@ namespace ARMeilleure.Translation
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Add(Instruction.LoadFromContext);
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Add(Instruction.LoadFromContext);
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}
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}
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public void MemoryBarrier()
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{
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Add(Instruction.MemoryBarrier);
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}
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public Operand Multiply(Operand op1, Operand op2)
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public Operand Multiply(Operand op1, Operand op2)
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{
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{
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return Add(Instruction.Multiply, Local(op1.Type), op1, op2);
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return Add(Instruction.Multiply, Local(op1.Type), op1, op2);
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@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
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private const string OuterHeaderMagicString = "PTCohd\0\0";
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private const string OuterHeaderMagicString = "PTCohd\0\0";
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private const string InnerHeaderMagicString = "PTCihd\0\0";
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private const string InnerHeaderMagicString = "PTCihd\0\0";
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private const uint InternalVersion = 2953; //! To be incremented manually for each change to the ARMeilleure project.
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private const uint InternalVersion = 3015; //! To be incremented manually for each change to the ARMeilleure project.
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private const string ActualDir = "0";
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private const string ActualDir = "0";
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private const string BackupDir = "1";
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private const string BackupDir = "1";
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