Commit graph

116 commits

Author SHA1 Message Date
emmauss
f2b9a9c2b0
Render Profiler in GUI (#854)
* move profiler output to gui

* addressed commits, rebased

* removed whitespaces
2020-02-06 11:25:47 +00:00
Ac_K
5facc0c07f Name all threads (#886)
* Name all threads

Close #874

* use ThreadName instead of ThreadId in Logging
2020-01-13 01:21:54 +01:00
gdkchan
b8e3909d80 Add a GetSpan method to the memory manager and use it on GPU (#877) 2020-01-13 10:27:50 +11:00
gdkchan
6cf9a04d98 Stop memory modification check when a invalid address is found 2020-01-09 02:13:00 +01:00
gdk
8cba252b23 Add per-source type memory change tracking, simplified state change tracking, other fixes 2020-01-09 02:13:00 +01:00
gdk
1876b346fe Initial work 2020-01-09 02:13:00 +01:00
LDj3SNuD
0915731a9d Implemented fast paths for: (#846)
* opt

* Nit.

* opt_p2

* Nit.
2019-12-29 22:22:47 -03:00
gdkchan
e5858e2c7d
Add a limit for the number of instructions in a function (#843) 2019-12-14 18:18:51 -03:00
LDj3SNuD
8c85bdf2ed Implemented fast paths for: (#841)
* cpu-misc_opt

* B = ~b

* ;
2019-12-07 13:45:32 +01:00
LDj3SNuD
7c111a3567 Add Mrs & Msr (Nzcv) Inst., with Tests. (#819)
* Add Mrs & Msr (Nzcv) Inst., with Tests.

* Don't use `NativeInterface`.
2019-11-14 13:08:07 +11:00
LDj3SNuD
eefe2b20fc Fix Fcmge_S/V & Fcmgt_S/V Inst.s (#815)
* Fix Fcmge_S/V & Fcmgt_S/V.

Follow-up Fcm**_S/V & Fc*mp*_S.
Improve CmpCondition enum.
Nits.

* Optimize Fccmp*_S & Fcmp*_S.

* Fix cvtsd2si opcode.

* Address PR feedback.
2019-11-09 23:21:03 -03:00
LDj3SNuD
eee639d6ba .NET Core 3.0 is here! (#784)
* .NET Core 3.0 is here!

* Remove IMemoryManager.cs and its references.

* Add T Math/F.FusedMultiplyAdd(T, T, T). Nits.

* Nit.

* Update appveyor.yml

* Revert "Resolve Visual Studio build issues"

This reverts commit 1772128ce0.

* Update SvcTable.cs
2019-10-31 19:09:03 +01:00
LDj3SNuD
eff8379d2a Add Sli_S/V & Sri_S/V inst.s (fast & slow paths), with Tests. (#797)
* Add Sli & Sri.

* Add scalar variants.
2019-10-24 20:37:42 -03:00
jduncanator
1772128ce0 Resolve Visual Studio build issues
Visual Studio defaults to a C# version of "latest major". Some of the new projects require C# 7.1 features.
2019-10-22 14:09:49 +11:00
LDj3SNuD
16869402bf Add Tbx Inst. (fast & slow paths), with Tests. (#782)
* Update OpCodeTable.cs

* Update InstName.cs

* Update InstEmitSimdMove.cs

* Update SoftFallback.cs

* Update DelegateTypes.cs

* Update CpuTestSimdTbl.cs

* Update CpuTest.cs

* Update Ryujinx.Tests.csproj

* Nit.
2019-10-04 11:43:20 -03:00
gdkchan
a731ab3a2a Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 21:56:22 +03:00