LDj3SNuD
|
8f6387128a
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
|
2018-06-25 22:32:29 -03:00 |
|
gdkchan
|
f9f111bc85
|
Add intrinsics support (#121)
* Initial intrinsics support
* Update tests to work with the new Vector128 type and intrinsics
* Drop SSE4.1 requirement
* Fix copy-paste mistake
|
2018-05-11 20:10:27 -03:00 |
|
gdkchan
|
bd9b1e2c6b
|
Stub a few services, add support for generating call stacks on the CPU
|
2018-04-22 01:22:46 -03:00 |
|
gdkchan
|
3777fb44cf
|
Allow to enable/disable memory checks even on release mode through the flag, return error for invalid addresses on SvcMap*Memory svcs, do not return error on SvcQueryMemory (instead, return reserved for the end of the address space), other minor tweaks
|
2018-03-10 20:39:16 -03:00 |
|
gdkchan
|
5912bd2beb
|
Disable memory checks by default, even on debug, move ram memory allocation inside the CPU, since the size if fixed anyway, better heap region size
|
2018-03-09 23:12:57 -03:00 |
|
emmauss
|
62b827f474
|
Split main project into core,graphics and chocolarm4 subproject (#29)
|
2018-02-20 17:09:23 -03:00 |
|