using Ryujinx.Memory; using System; using System.Runtime.CompilerServices; using System.Runtime.InteropServices; namespace Ryujinx.Graphics.Gpu.Memory { /// /// GPU memory manager. /// public class MemoryManager { private const int PtLvl0Bits = 14; private const int PtLvl1Bits = 14; public const int PtPageBits = 12; private const ulong PtLvl0Size = 1UL << PtLvl0Bits; private const ulong PtLvl1Size = 1UL << PtLvl1Bits; public const ulong PageSize = 1UL << PtPageBits; private const ulong PtLvl0Mask = PtLvl0Size - 1; private const ulong PtLvl1Mask = PtLvl1Size - 1; public const ulong PageMask = PageSize - 1; private const int PtLvl0Bit = PtPageBits + PtLvl1Bits; private const int PtLvl1Bit = PtPageBits; public const ulong PteUnmapped = 0xffffffff_ffffffff; private readonly ulong[][] _pageTable; public event EventHandler MemoryUnmapped; private GpuContext _context; /// /// Creates a new instance of the GPU memory manager. /// public MemoryManager(GpuContext context) { _context = context; _pageTable = new ulong[PtLvl0Size][]; } /// /// Reads data from GPU mapped memory. /// /// Type of the data /// GPU virtual address where the data is located /// The data at the specified memory location public T Read(ulong gpuVa) where T : unmanaged { ulong processVa = Translate(gpuVa); return MemoryMarshal.Cast(_context.PhysicalMemory.GetSpan(processVa, Unsafe.SizeOf()))[0]; } /// /// Gets a read-only span of data from GPU mapped memory. /// /// GPU virtual address where the data is located /// Size of the data /// The span of the data at the specified memory location public ReadOnlySpan GetSpan(ulong gpuVa, int size) { ulong processVa = Translate(gpuVa); return _context.PhysicalMemory.GetSpan(processVa, size); } /// /// Gets a writable region from GPU mapped memory. /// /// Start address of the range /// Size in bytes to be range /// A writable region with the data at the specified memory location public WritableRegion GetWritableRegion(ulong gpuVa, int size) { ulong processVa = Translate(gpuVa); return _context.PhysicalMemory.GetWritableRegion(processVa, size); } /// /// Writes data to GPU mapped memory. /// /// Type of the data /// GPU virtual address to write the value into /// The value to be written public void Write(ulong gpuVa, T value) where T : unmanaged { ulong processVa = Translate(gpuVa); _context.PhysicalMemory.Write(processVa, MemoryMarshal.Cast(MemoryMarshal.CreateSpan(ref value, 1))); } /// /// Writes data to GPU mapped memory. /// /// GPU virtual address to write the data into /// The data to be written public void Write(ulong gpuVa, ReadOnlySpan data) { ulong processVa = Translate(gpuVa); _context.PhysicalMemory.Write(processVa, data); } /// /// Maps a given range of pages to the specified CPU virtual address. /// /// /// All addresses and sizes must be page aligned. /// /// CPU virtual address to map into /// GPU virtual address to be mapped /// Size in bytes of the mapping public void Map(ulong pa, ulong va, ulong size) { lock (_pageTable) { MemoryUnmapped?.Invoke(this, new UnmapEventArgs(va, size)); for (ulong offset = 0; offset < size; offset += PageSize) { SetPte(va + offset, pa + offset); } } } /// /// Unmaps a given range of pages at the specified GPU virtual memory region. /// /// GPU virtual address to unmap /// Size in bytes of the region being unmapped public void Unmap(ulong va, ulong size) { lock (_pageTable) { // Event handlers are not expected to be thread safe. MemoryUnmapped?.Invoke(this, new UnmapEventArgs(va, size)); for (ulong offset = 0; offset < size; offset += PageSize) { SetPte(va + offset, PteUnmapped); } } } /// /// Checks if a given page is mapped. /// /// GPU virtual address of the page to check /// True if the page is mapped, false otherwise public bool IsMapped(ulong gpuVa) { return Translate(gpuVa) != PteUnmapped; } /// /// Translates a GPU virtual address to a CPU virtual address. /// /// GPU virtual address to be translated /// CPU virtual address public ulong Translate(ulong gpuVa) { ulong baseAddress = GetPte(gpuVa); if (baseAddress == PteUnmapped) { return PteUnmapped; } return baseAddress + (gpuVa & PageMask); } /// /// Gets the Page Table entry for a given GPU virtual address. /// /// GPU virtual address /// Page table entry (CPU virtual address) private ulong GetPte(ulong gpuVa) { ulong l0 = (gpuVa >> PtLvl0Bit) & PtLvl0Mask; ulong l1 = (gpuVa >> PtLvl1Bit) & PtLvl1Mask; if (_pageTable[l0] == null) { return PteUnmapped; } return _pageTable[l0][l1]; } /// /// Sets a Page Table entry at a given GPU virtual address. /// /// GPU virtual address /// Page table entry (CPU virtual address) private void SetPte(ulong gpuVa, ulong pte) { ulong l0 = (gpuVa >> PtLvl0Bit) & PtLvl0Mask; ulong l1 = (gpuVa >> PtLvl1Bit) & PtLvl1Mask; if (_pageTable[l0] == null) { _pageTable[l0] = new ulong[PtLvl1Size]; for (ulong index = 0; index < PtLvl1Size; index++) { _pageTable[l0][index] = PteUnmapped; } } _pageTable[l0][l1] = pte; } } }