mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-19 23:28:42 +02:00
* Better implementation of the DMA pusher, misc fixes * Remove some debug code * Correct RGBX8 format * Add support for linked Texture Sampler Control * Attempt to fix upside down screen issue
187 lines
6.1 KiB
C#
187 lines
6.1 KiB
C#
using Ryujinx.Graphics.Memory;
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using Ryujinx.Graphics.Texture;
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using System.Collections.Generic;
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namespace Ryujinx.Graphics
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{
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class NvGpuEngineM2mf : INvGpuEngine
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{
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public int[] Registers { get; private set; }
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private NvGpu Gpu;
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private Dictionary<int, NvGpuMethod> Methods;
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public NvGpuEngineM2mf(NvGpu Gpu)
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{
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this.Gpu = Gpu;
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Registers = new int[0x1d6];
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Methods = new Dictionary<int, NvGpuMethod>();
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void AddMethod(int Meth, int Count, int Stride, NvGpuMethod Method)
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{
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while (Count-- > 0)
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{
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Methods.Add(Meth, Method);
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Meth += Stride;
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}
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}
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AddMethod(0xc0, 1, 1, Execute);
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}
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public void CallMethod(NvGpuVmm Vmm, GpuMethodCall MethCall)
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{
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if (Methods.TryGetValue(MethCall.Method, out NvGpuMethod Method))
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{
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Method(Vmm, MethCall);
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}
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else
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{
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WriteRegister(MethCall);
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}
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}
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private void Execute(NvGpuVmm Vmm, GpuMethodCall MethCall)
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{
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//TODO: Some registers and copy modes are still not implemented.
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int Control = MethCall.Argument;
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bool SrcLinear = ((Control >> 7) & 1) != 0;
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bool DstLinear = ((Control >> 8) & 1) != 0;
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bool Copy2d = ((Control >> 9) & 1) != 0;
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long SrcAddress = MakeInt64From2xInt32(NvGpuEngineM2mfReg.SrcAddress);
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long DstAddress = MakeInt64From2xInt32(NvGpuEngineM2mfReg.DstAddress);
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int SrcPitch = ReadRegister(NvGpuEngineM2mfReg.SrcPitch);
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int DstPitch = ReadRegister(NvGpuEngineM2mfReg.DstPitch);
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int XCount = ReadRegister(NvGpuEngineM2mfReg.XCount);
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int YCount = ReadRegister(NvGpuEngineM2mfReg.YCount);
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int Swizzle = ReadRegister(NvGpuEngineM2mfReg.Swizzle);
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int DstBlkDim = ReadRegister(NvGpuEngineM2mfReg.DstBlkDim);
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int DstSizeX = ReadRegister(NvGpuEngineM2mfReg.DstSizeX);
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int DstSizeY = ReadRegister(NvGpuEngineM2mfReg.DstSizeY);
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int DstSizeZ = ReadRegister(NvGpuEngineM2mfReg.DstSizeZ);
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int DstPosXY = ReadRegister(NvGpuEngineM2mfReg.DstPosXY);
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int DstPosZ = ReadRegister(NvGpuEngineM2mfReg.DstPosZ);
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int SrcBlkDim = ReadRegister(NvGpuEngineM2mfReg.SrcBlkDim);
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int SrcSizeX = ReadRegister(NvGpuEngineM2mfReg.SrcSizeX);
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int SrcSizeY = ReadRegister(NvGpuEngineM2mfReg.SrcSizeY);
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int SrcSizeZ = ReadRegister(NvGpuEngineM2mfReg.SrcSizeZ);
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int SrcPosXY = ReadRegister(NvGpuEngineM2mfReg.SrcPosXY);
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int SrcPosZ = ReadRegister(NvGpuEngineM2mfReg.SrcPosZ);
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int SrcCpp = ((Swizzle >> 20) & 7) + 1;
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int DstCpp = ((Swizzle >> 24) & 7) + 1;
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int DstPosX = (DstPosXY >> 0) & 0xffff;
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int DstPosY = (DstPosXY >> 16) & 0xffff;
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int SrcPosX = (SrcPosXY >> 0) & 0xffff;
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int SrcPosY = (SrcPosXY >> 16) & 0xffff;
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int SrcBlockHeight = 1 << ((SrcBlkDim >> 4) & 0xf);
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int DstBlockHeight = 1 << ((DstBlkDim >> 4) & 0xf);
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long SrcPA = Vmm.GetPhysicalAddress(SrcAddress);
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long DstPA = Vmm.GetPhysicalAddress(DstAddress);
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if (Copy2d)
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{
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if (SrcLinear)
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{
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SrcPosX = SrcPosY = SrcPosZ = 0;
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}
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if (DstLinear)
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{
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DstPosX = DstPosY = DstPosZ = 0;
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}
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if (SrcLinear && DstLinear)
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{
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for (int Y = 0; Y < YCount; Y++)
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{
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int SrcOffset = (SrcPosY + Y) * SrcPitch + SrcPosX * SrcCpp;
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int DstOffset = (DstPosY + Y) * DstPitch + DstPosX * DstCpp;
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long Src = SrcPA + (uint)SrcOffset;
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long Dst = DstPA + (uint)DstOffset;
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Vmm.Memory.CopyBytes(Src, Dst, XCount * SrcCpp);
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}
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}
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else
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{
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ISwizzle SrcSwizzle;
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if (SrcLinear)
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{
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SrcSwizzle = new LinearSwizzle(SrcPitch, SrcCpp);
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}
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else
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{
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SrcSwizzle = new BlockLinearSwizzle(SrcSizeX, SrcCpp, SrcBlockHeight);
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}
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ISwizzle DstSwizzle;
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if (DstLinear)
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{
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DstSwizzle = new LinearSwizzle(DstPitch, DstCpp);
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}
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else
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{
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DstSwizzle = new BlockLinearSwizzle(DstSizeX, DstCpp, DstBlockHeight);
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}
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for (int Y = 0; Y < YCount; Y++)
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for (int X = 0; X < XCount; X++)
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{
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int SrcOffset = SrcSwizzle.GetSwizzleOffset(SrcPosX + X, SrcPosY + Y);
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int DstOffset = DstSwizzle.GetSwizzleOffset(DstPosX + X, DstPosY + Y);
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long Src = SrcPA + (uint)SrcOffset;
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long Dst = DstPA + (uint)DstOffset;
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Vmm.Memory.CopyBytes(Src, Dst, SrcCpp);
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}
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}
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}
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else
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{
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Vmm.Memory.CopyBytes(SrcPA, DstPA, XCount);
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}
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}
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private long MakeInt64From2xInt32(NvGpuEngineM2mfReg Reg)
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{
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return
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(long)Registers[(int)Reg + 0] << 32 |
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(uint)Registers[(int)Reg + 1];
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}
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private void WriteRegister(GpuMethodCall MethCall)
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{
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Registers[MethCall.Method] = MethCall.Argument;
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}
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private int ReadRegister(NvGpuEngineM2mfReg Reg)
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{
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return Registers[(int)Reg];
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}
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private void WriteRegister(NvGpuEngineM2mfReg Reg, int Value)
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{
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Registers[(int)Reg] = Value;
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}
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}
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} |