mirror of
https://github.com/Ryujinx/Ryujinx.git
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* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
311 lines
9.3 KiB
C#
311 lines
9.3 KiB
C#
using Ryujinx.Tests.Unicorn.Native;
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using System;
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namespace Ryujinx.Tests.Unicorn
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{
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public class UnicornAArch64
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{
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internal readonly IntPtr uc;
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public IndexedProperty<int, ulong> X
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{
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get
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{
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return new IndexedProperty<int, ulong>(
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(int i) => GetX(i),
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(int i, ulong value) => SetX(i, value));
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}
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}
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public IndexedProperty<int, SimdValue> Q
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{
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get
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{
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return new IndexedProperty<int, SimdValue>(
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(int i) => GetQ(i),
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(int i, SimdValue value) => SetQ(i, value));
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}
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}
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public ulong LR
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{
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get => GetRegister(ArmRegister.LR);
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set => SetRegister(ArmRegister.LR, value);
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}
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public ulong SP
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{
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get => GetRegister(ArmRegister.SP);
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set => SetRegister(ArmRegister.SP, value);
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}
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public ulong PC
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{
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get => GetRegister(ArmRegister.PC);
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set => SetRegister(ArmRegister.PC, value);
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}
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public uint Pstate
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{
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get => (uint)GetRegister(ArmRegister.PSTATE);
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set => SetRegister(ArmRegister.PSTATE, (uint)value);
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}
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public int Fpcr
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{
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get => (int)GetRegister(ArmRegister.FPCR);
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set => SetRegister(ArmRegister.FPCR, (uint)value);
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}
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public int Fpsr
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{
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get => (int)GetRegister(ArmRegister.FPSR);
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set => SetRegister(ArmRegister.FPSR, (uint)value);
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}
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public bool OverflowFlag
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{
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get => (Pstate & 0x10000000u) != 0;
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set => Pstate = (Pstate & ~0x10000000u) | (value ? 0x10000000u : 0u);
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}
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public bool CarryFlag
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{
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get => (Pstate & 0x20000000u) != 0;
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set => Pstate = (Pstate & ~0x20000000u) | (value ? 0x20000000u : 0u);
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}
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public bool ZeroFlag
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{
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get => (Pstate & 0x40000000u) != 0;
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set => Pstate = (Pstate & ~0x40000000u) | (value ? 0x40000000u : 0u);
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}
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public bool NegativeFlag
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{
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get => (Pstate & 0x80000000u) != 0;
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set => Pstate = (Pstate & ~0x80000000u) | (value ? 0x80000000u : 0u);
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}
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public UnicornAArch64()
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{
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Interface.Checked(Interface.uc_open(UnicornArch.UC_ARCH_ARM64, UnicornMode.UC_MODE_LITTLE_ENDIAN, out uc));
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SetRegister(ArmRegister.CPACR_EL1, 0x00300000);
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}
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~UnicornAArch64()
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{
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Interface.Checked(Native.Interface.uc_close(uc));
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}
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public void RunForCount(ulong count)
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{
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Interface.Checked(Native.Interface.uc_emu_start(uc, this.PC, 0xFFFFFFFFFFFFFFFFu, 0, count));
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}
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public void Step()
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{
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RunForCount(1);
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}
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private static ArmRegister[] XRegisters = new ArmRegister[31]
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{
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ArmRegister.X0,
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ArmRegister.X1,
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ArmRegister.X2,
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ArmRegister.X3,
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ArmRegister.X4,
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ArmRegister.X5,
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ArmRegister.X6,
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ArmRegister.X7,
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ArmRegister.X8,
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ArmRegister.X9,
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ArmRegister.X10,
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ArmRegister.X11,
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ArmRegister.X12,
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ArmRegister.X13,
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ArmRegister.X14,
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ArmRegister.X15,
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ArmRegister.X16,
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ArmRegister.X17,
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ArmRegister.X18,
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ArmRegister.X19,
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ArmRegister.X20,
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ArmRegister.X21,
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ArmRegister.X22,
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ArmRegister.X23,
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ArmRegister.X24,
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ArmRegister.X25,
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ArmRegister.X26,
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ArmRegister.X27,
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ArmRegister.X28,
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ArmRegister.X29,
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ArmRegister.X30,
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};
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private static ArmRegister[] QRegisters = new ArmRegister[32]
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{
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ArmRegister.Q0,
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ArmRegister.Q1,
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ArmRegister.Q2,
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ArmRegister.Q3,
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ArmRegister.Q4,
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ArmRegister.Q5,
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ArmRegister.Q6,
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ArmRegister.Q7,
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ArmRegister.Q8,
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ArmRegister.Q9,
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ArmRegister.Q10,
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ArmRegister.Q11,
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ArmRegister.Q12,
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ArmRegister.Q13,
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ArmRegister.Q14,
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ArmRegister.Q15,
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ArmRegister.Q16,
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ArmRegister.Q17,
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ArmRegister.Q18,
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ArmRegister.Q19,
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ArmRegister.Q20,
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ArmRegister.Q21,
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ArmRegister.Q22,
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ArmRegister.Q23,
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ArmRegister.Q24,
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ArmRegister.Q25,
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ArmRegister.Q26,
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ArmRegister.Q27,
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ArmRegister.Q28,
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ArmRegister.Q29,
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ArmRegister.Q30,
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ArmRegister.Q31,
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};
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public ulong GetX(int index)
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{
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if ((uint)index > 30)
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{
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throw new ArgumentOutOfRangeException(nameof(index));
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}
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return GetRegister(XRegisters[index]);
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}
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public void SetX(int index, ulong value)
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{
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if ((uint)index > 30)
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{
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throw new ArgumentOutOfRangeException(nameof(index));
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}
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SetRegister(XRegisters[index], value);
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}
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public SimdValue GetQ(int index)
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{
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if ((uint)index > 31)
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{
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throw new ArgumentOutOfRangeException(nameof(index));
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}
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return GetVector(QRegisters[index]);
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}
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public void SetQ(int index, SimdValue value)
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{
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if ((uint)index > 31)
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{
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throw new ArgumentOutOfRangeException(nameof(index));
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}
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SetVector(QRegisters[index], value);
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}
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private ulong GetRegister(ArmRegister register)
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{
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byte[] data = new byte[8];
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Interface.Checked(Native.Interface.uc_reg_read(uc, (int)register, data));
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return (ulong)BitConverter.ToInt64(data, 0);
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}
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private void SetRegister(ArmRegister register, ulong value)
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{
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byte[] data = BitConverter.GetBytes(value);
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Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
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}
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private SimdValue GetVector(ArmRegister register)
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{
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byte[] data = new byte[16];
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Interface.Checked(Interface.uc_reg_read(uc, (int)register, data));
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return new SimdValue(data);
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}
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private void SetVector(ArmRegister register, SimdValue value)
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{
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byte[] data = value.ToArray();
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Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
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}
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public byte[] MemoryRead(ulong address, ulong size)
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{
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byte[] value = new byte[size];
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Interface.Checked(Interface.uc_mem_read(uc, address, value, size));
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return value;
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}
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public byte MemoryRead8 (ulong address) => MemoryRead(address, 1)[0];
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public UInt16 MemoryRead16(ulong address) => (UInt16)BitConverter.ToInt16(MemoryRead(address, 2), 0);
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public UInt32 MemoryRead32(ulong address) => (UInt32)BitConverter.ToInt32(MemoryRead(address, 4), 0);
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public UInt64 MemoryRead64(ulong address) => (UInt64)BitConverter.ToInt64(MemoryRead(address, 8), 0);
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public void MemoryWrite(ulong address, byte[] value)
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{
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Interface.Checked(Interface.uc_mem_write(uc, address, value, (ulong)value.Length));
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}
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public void MemoryWrite8 (ulong address, byte value) => MemoryWrite(address, new byte[]{value});
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public void MemoryWrite16(ulong address, Int16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
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public void MemoryWrite16(ulong address, UInt16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
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public void MemoryWrite32(ulong address, Int32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
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public void MemoryWrite32(ulong address, UInt32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
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public void MemoryWrite64(ulong address, Int64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
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public void MemoryWrite64(ulong address, UInt64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
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public void MemoryMap(ulong address, ulong size, MemoryPermission permissions)
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{
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Interface.Checked(Interface.uc_mem_map(uc, address, size, (uint)permissions));
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}
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public void MemoryUnmap(ulong address, ulong size)
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{
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Interface.Checked(Interface.uc_mem_unmap(uc, address, size));
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}
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public void MemoryProtect(ulong address, ulong size, MemoryPermission permissions)
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{
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Interface.Checked(Interface.uc_mem_protect(uc, address, size, (uint)permissions));
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}
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public static bool IsAvailable()
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{
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try
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{
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Interface.uc_version(out _, out _);
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return true;
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}
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catch (DllNotFoundException)
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{
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return false;
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}
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}
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}
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} |