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https://github.com/Ryujinx/Ryujinx.git
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* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
159 lines
4.8 KiB
C#
159 lines
4.8 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitFlowHelper;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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public static void B(ArmEmitterContext context)
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{
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OpCodeBImmAl op = (OpCodeBImmAl)context.CurrOp;
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if (context.CurrBlock.Branch != null)
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{
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context.Branch(context.GetLabel((ulong)op.Immediate));
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}
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else
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{
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context.Return(Const(op.Immediate));
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}
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}
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public static void B_Cond(ArmEmitterContext context)
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{
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OpCodeBImmCond op = (OpCodeBImmCond)context.CurrOp;
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EmitBranch(context, op.Cond);
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}
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public static void Bl(ArmEmitterContext context)
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{
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OpCodeBImmAl op = (OpCodeBImmAl)context.CurrOp;
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context.Copy(GetIntOrZR(context, RegisterAlias.Lr), Const(op.Address + 4));
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EmitCall(context, (ulong)op.Immediate);
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}
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public static void Blr(ArmEmitterContext context)
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{
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OpCodeBReg op = (OpCodeBReg)context.CurrOp;
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Operand n = context.Copy(GetIntOrZR(context, op.Rn));
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context.Copy(GetIntOrZR(context, RegisterAlias.Lr), Const(op.Address + 4));
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EmitVirtualCall(context, n);
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}
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public static void Br(ArmEmitterContext context)
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{
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OpCodeBReg op = (OpCodeBReg)context.CurrOp;
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EmitVirtualJump(context, GetIntOrZR(context, op.Rn));
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}
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public static void Cbnz(ArmEmitterContext context) => EmitCb(context, onNotZero: true);
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public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false);
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private static void EmitCb(ArmEmitterContext context, bool onNotZero)
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{
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OpCodeBImmCmp op = (OpCodeBImmCmp)context.CurrOp;
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EmitBranch(context, GetIntOrZR(context, op.Rt), onNotZero);
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}
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public static void Ret(ArmEmitterContext context)
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{
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context.Return(context.BitwiseOr(GetIntOrZR(context, RegisterAlias.Lr), Const(CallFlag)));
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}
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public static void Tbnz(ArmEmitterContext context) => EmitTb(context, onNotZero: true);
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public static void Tbz(ArmEmitterContext context) => EmitTb(context, onNotZero: false);
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private static void EmitTb(ArmEmitterContext context, bool onNotZero)
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{
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OpCodeBImmTest op = (OpCodeBImmTest)context.CurrOp;
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Operand value = context.BitwiseAnd(GetIntOrZR(context, op.Rt), Const(1L << op.Bit));
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EmitBranch(context, value, onNotZero);
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}
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private static void EmitBranch(ArmEmitterContext context, Condition cond)
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{
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OpCodeBImm op = (OpCodeBImm)context.CurrOp;
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if (context.CurrBlock.Branch != null)
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{
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EmitCondBranch(context, context.GetLabel((ulong)op.Immediate), cond);
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if (context.CurrBlock.Next == null)
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{
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context.Return(Const(op.Address + 4));
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}
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}
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else
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{
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Operand lblTaken = Label();
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EmitCondBranch(context, lblTaken, cond);
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context.Return(Const(op.Address + 4));
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context.MarkLabel(lblTaken);
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context.Return(Const(op.Immediate));
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}
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}
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private static void EmitBranch(ArmEmitterContext context, Operand value, bool onNotZero)
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{
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OpCodeBImm op = (OpCodeBImm)context.CurrOp;
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if (context.CurrBlock.Branch != null)
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{
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Operand lblTarget = context.GetLabel((ulong)op.Immediate);
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if (onNotZero)
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{
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context.BranchIfTrue(lblTarget, value);
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}
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else
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{
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context.BranchIfFalse(lblTarget, value);
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}
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if (context.CurrBlock.Next == null)
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{
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context.Return(Const(op.Address + 4));
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}
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}
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else
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{
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Operand lblTaken = Label();
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if (onNotZero)
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{
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context.BranchIfTrue(lblTaken, value);
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}
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else
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{
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context.BranchIfFalse(lblTaken, value);
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}
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context.Return(Const(op.Address + 4));
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context.MarkLabel(lblTaken);
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context.Return(Const(op.Immediate));
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}
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}
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}
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} |