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https://github.com/Ryujinx/Ryujinx.git
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* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
256 lines
7.6 KiB
C#
256 lines
7.6 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitMemoryHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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private const int ByteSizeLog2 = 0;
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private const int HWordSizeLog2 = 1;
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private const int WordSizeLog2 = 2;
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private const int DWordSizeLog2 = 3;
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[Flags]
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enum AccessType
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{
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Store = 0,
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Signed = 1,
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Load = 2,
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LoadZx = Load,
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LoadSx = Load | Signed,
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}
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public static void Ldm(ArmEmitterContext context)
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{
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OpCode32MemMult op = (OpCode32MemMult)context.CurrOp;
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Operand n = GetIntA32(context, op.Rn);
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Operand baseAddress = context.Add(n, Const(op.Offset));
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bool writesToPc = (op.RegisterMask & (1 << RegisterAlias.Aarch32Pc)) != 0;
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bool writeBack = op.PostOffset != 0 && (op.Rn != RegisterAlias.Aarch32Pc || !writesToPc);
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if (writeBack)
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{
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SetIntA32(context, op.Rn, context.Add(n, Const(op.PostOffset)));
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}
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int mask = op.RegisterMask;
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int offset = 0;
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for (int register = 0; mask != 0; mask >>= 1, register++)
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{
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if ((mask & 1) != 0)
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{
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Operand address = context.Add(baseAddress, Const(offset));
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EmitLoadZx(context, address, register, WordSizeLog2);
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offset += 4;
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}
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}
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}
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public static void Ldr(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, WordSizeLog2, AccessType.LoadZx);
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}
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public static void Ldrb(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, ByteSizeLog2, AccessType.LoadZx);
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}
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public static void Ldrd(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, DWordSizeLog2, AccessType.LoadZx);
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}
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public static void Ldrh(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, HWordSizeLog2, AccessType.LoadZx);
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}
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public static void Ldrsb(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, ByteSizeLog2, AccessType.LoadSx);
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}
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public static void Ldrsh(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, HWordSizeLog2, AccessType.LoadSx);
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}
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public static void Stm(ArmEmitterContext context)
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{
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OpCode32MemMult op = (OpCode32MemMult)context.CurrOp;
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Operand n = GetIntA32(context, op.Rn);
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Operand baseAddress = context.Add(n, Const(op.Offset));
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int mask = op.RegisterMask;
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int offset = 0;
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for (int register = 0; mask != 0; mask >>= 1, register++)
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{
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if ((mask & 1) != 0)
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{
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Operand address = context.Add(baseAddress, Const(offset));
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EmitStore(context, address, register, WordSizeLog2);
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// Note: If Rn is also specified on the register list,
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// and Rn is the first register on this list, then the
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// value that is written to memory is the unmodified value,
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// before the write back. If it is on the list, but it's
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// not the first one, then the value written to memory
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// varies between CPUs.
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if (offset == 0 && op.PostOffset != 0)
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{
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// Emit write back after the first write.
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SetIntA32(context, op.Rn, context.Add(n, Const(op.PostOffset)));
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}
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offset += 4;
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}
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}
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}
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public static void Str(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, WordSizeLog2, AccessType.Store);
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}
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public static void Strb(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, ByteSizeLog2, AccessType.Store);
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}
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public static void Strd(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, DWordSizeLog2, AccessType.Store);
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}
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public static void Strh(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, HWordSizeLog2, AccessType.Store);
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}
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private static void EmitLoadOrStore(ArmEmitterContext context, int size, AccessType accType)
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{
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OpCode32Mem op = (OpCode32Mem)context.CurrOp;
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Operand n = context.Copy(GetIntA32(context, op.Rn));
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Operand temp = null;
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if (op.Index || op.WBack)
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{
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temp = op.Add
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? context.Add (n, Const(op.Immediate))
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: context.Subtract(n, Const(op.Immediate));
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}
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if (op.WBack)
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{
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SetIntA32(context, op.Rn, temp);
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}
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Operand address;
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if (op.Index)
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{
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address = temp;
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}
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else
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{
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address = n;
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}
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if ((accType & AccessType.Load) != 0)
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{
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void Load(int rt, int offs, int loadSize)
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{
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Operand addr = context.Add(address, Const(offs));
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if ((accType & AccessType.Signed) != 0)
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{
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EmitLoadSx32(context, addr, rt, loadSize);
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}
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else
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{
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EmitLoadZx(context, addr, rt, loadSize);
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}
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}
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if (size == DWordSizeLog2)
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{
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Operand lblBigEndian = Label();
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Operand lblEnd = Label();
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context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
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Load(op.Rt, 0, WordSizeLog2);
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Load(op.Rt | 1, 4, WordSizeLog2);
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context.Branch(lblEnd);
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context.MarkLabel(lblBigEndian);
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Load(op.Rt | 1, 0, WordSizeLog2);
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Load(op.Rt, 4, WordSizeLog2);
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context.MarkLabel(lblEnd);
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}
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else
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{
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Load(op.Rt, 0, size);
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}
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}
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else
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{
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void Store(int rt, int offs, int storeSize)
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{
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Operand addr = context.Add(address, Const(offs));
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EmitStore(context, addr, rt, storeSize);
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}
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if (size == DWordSizeLog2)
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{
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Operand lblBigEndian = Label();
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Operand lblEnd = Label();
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context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
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Store(op.Rt, 0, WordSizeLog2);
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Store(op.Rt | 1, 4, WordSizeLog2);
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context.Branch(lblEnd);
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context.MarkLabel(lblBigEndian);
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Store(op.Rt | 1, 0, WordSizeLog2);
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Store(op.Rt, 4, WordSizeLog2);
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context.MarkLabel(lblEnd);
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}
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else
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{
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Store(op.Rt, 0, size);
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}
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}
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}
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}
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} |