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https://github.com/Ryujinx/Ryujinx.git
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* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
160 lines
4.5 KiB
C#
160 lines
4.5 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitMemoryHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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public static void Ld__Vms(ArmEmitterContext context)
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{
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EmitSimdMemMs(context, isLoad: true);
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}
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public static void Ld__Vss(ArmEmitterContext context)
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{
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EmitSimdMemSs(context, isLoad: true);
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}
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public static void St__Vms(ArmEmitterContext context)
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{
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EmitSimdMemMs(context, isLoad: false);
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}
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public static void St__Vss(ArmEmitterContext context)
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{
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EmitSimdMemSs(context, isLoad: false);
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}
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private static void EmitSimdMemMs(ArmEmitterContext context, bool isLoad)
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{
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OpCodeSimdMemMs op = (OpCodeSimdMemMs)context.CurrOp;
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Operand n = GetIntOrSP(context, op.Rn);
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long offset = 0;
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for (int rep = 0; rep < op.Reps; rep++)
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for (int elem = 0; elem < op.Elems; elem++)
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for (int sElem = 0; sElem < op.SElems; sElem++)
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{
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int rtt = (op.Rt + rep + sElem) & 0x1f;
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Operand tt = GetVec(rtt);
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Operand address = context.Add(n, Const(offset));
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if (isLoad)
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{
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EmitLoadSimd(context, address, tt, rtt, elem, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64 && elem == op.Elems - 1)
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{
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context.Copy(tt, context.VectorZeroUpper64(tt));
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}
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}
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else
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{
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EmitStoreSimd(context, address, rtt, elem, op.Size);
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}
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offset += 1 << op.Size;
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}
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if (op.WBack)
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{
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EmitSimdMemWBack(context, offset);
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}
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}
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private static void EmitSimdMemSs(ArmEmitterContext context, bool isLoad)
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{
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OpCodeSimdMemSs op = (OpCodeSimdMemSs)context.CurrOp;
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Operand n = GetIntOrSP(context, op.Rn);
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long offset = 0;
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if (op.Replicate)
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{
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// Only loads uses the replicate mode.
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Debug.Assert(isLoad, "Replicate mode is not valid for stores.");
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int elems = op.GetBytesCount() >> op.Size;
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for (int sElem = 0; sElem < op.SElems; sElem++)
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{
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int rt = (op.Rt + sElem) & 0x1f;
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Operand t = GetVec(rt);
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Operand address = context.Add(n, Const(offset));
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for (int index = 0; index < elems; index++)
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{
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EmitLoadSimd(context, address, t, rt, index, op.Size);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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context.Copy(t, context.VectorZeroUpper64(t));
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}
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offset += 1 << op.Size;
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}
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}
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else
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{
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for (int sElem = 0; sElem < op.SElems; sElem++)
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{
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int rt = (op.Rt + sElem) & 0x1f;
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Operand t = GetVec(rt);
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Operand address = context.Add(n, Const(offset));
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if (isLoad)
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{
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EmitLoadSimd(context, address, t, rt, op.Index, op.Size);
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}
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else
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{
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EmitStoreSimd(context, address, rt, op.Index, op.Size);
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}
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offset += 1 << op.Size;
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}
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}
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if (op.WBack)
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{
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EmitSimdMemWBack(context, offset);
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}
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}
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private static void EmitSimdMemWBack(ArmEmitterContext context, long offset)
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{
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OpCodeMemReg op = (OpCodeMemReg)context.CurrOp;
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Operand n = GetIntOrSP(context, op.Rn);
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Operand m;
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if (op.Rm != RegisterAlias.Zr)
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{
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m = GetIntOrZR(context, op.Rm);
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}
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else
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{
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m = Const(offset);
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}
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context.Copy(n, context.Add(n, m));
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}
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}
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} |