e21ebbf666
* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0 * Refactoring * Add a config entry to enable or disable the reg load/store opt. * Remove unnecessary register state stores for calls when the callee is know * Rename IoType to VarType * Enable tier 0 while fixing some perf issues related to tier 0 * Small tweak -- Compile before adding to the cache, to avoid lags * Add required config entry
51 lines
No EOL
1.6 KiB
C#
51 lines
No EOL
1.6 KiB
C#
using ChocolArm64.State;
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using System.Reflection.Emit;
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namespace ChocolArm64.Translation
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{
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struct ILOpCodeLoadState : IILEmit
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{
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private ILBlock _block;
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private bool _isSubEntry;
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public ILOpCodeLoadState(ILBlock block, bool isSubEntry = false)
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{
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_block = block;
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_isSubEntry = isSubEntry;
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}
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public void Emit(ILMethodBuilder context)
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{
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long intInputs = context.RegUsage.GetIntInputs(_block);
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long vecInputs = context.RegUsage.GetVecInputs(_block);
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if (Optimizations.AssumeStrictAbiCompliance && context.IsSubComplete)
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{
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intInputs = RegisterUsage.ClearCallerSavedIntRegs(intInputs, context.IsAarch64);
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vecInputs = RegisterUsage.ClearCallerSavedVecRegs(vecInputs, context.IsAarch64);
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}
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LoadLocals(context, intInputs, RegisterType.Int);
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LoadLocals(context, vecInputs, RegisterType.Vector);
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}
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private void LoadLocals(ILMethodBuilder context, long inputs, RegisterType baseType)
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{
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for (int bit = 0; bit < 64; bit++)
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{
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long mask = 1L << bit;
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if ((inputs & mask) != 0)
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{
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Register reg = ILMethodBuilder.GetRegFromBit(bit, baseType);
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context.Generator.EmitLdarg(TranslatedSub.StateArgIdx);
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context.Generator.Emit(OpCodes.Ldfld, reg.GetField());
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context.Generator.EmitStloc(context.GetLocalIndex(reg));
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}
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}
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}
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}
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} |