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* Add tests * Add some simple Alu instruction tests * travis: Run tests * CpuTest: Add TearDown
66 lines
2.1 KiB
C#
66 lines
2.1 KiB
C#
using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[TestFixture]
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public partial class CpuTest
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{
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[Test]
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public void Add()
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{
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// ADD X0, X1, X2
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ARegisters Registers = SingleOpcode(0x8B020020, X1: 1, X2: 2);
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Assert.AreEqual(3, Registers.X0);
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}
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[Test]
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public void Ands()
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{
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// ANDS W0, W1, W2
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uint Opcode = 0x6A020020;
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var tests = new[]
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{
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new { W1 = 0xFFFFFFFFul, W2 = 0xFFFFFFFFul, Result = 0xFFFFFFFFul, Negative = true, Zero = false },
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new { W1 = 0xFFFFFFFFul, W2 = 0x00000000ul, Result = 0x00000000ul, Negative = false, Zero = true },
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new { W1 = 0x12345678ul, W2 = 0x7324A993ul, Result = 0x12240010ul, Negative = false, Zero = false },
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};
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foreach (var test in tests)
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{
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ARegisters Registers = SingleOpcode(Opcode, X1: test.W1, X2: test.W2);
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Assert.AreEqual(test.Result, Registers.X0);
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Assert.AreEqual(test.Negative, Registers.Negative);
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Assert.AreEqual(test.Zero, Registers.Zero);
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}
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}
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[Test]
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public void OrrBitmasks()
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{
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// ORR W0, WZR, #0x01010101
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Assert.AreEqual(0x01010101, SingleOpcode(0x3200C3E0).X0);
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// ORR W1, WZR, #0x00F000F0
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Assert.AreEqual(0x00F000F0, SingleOpcode(0x320C8FE1).X1);
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// ORR W2, WZR, #1
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Assert.AreEqual(0x00000001, SingleOpcode(0x320003E2).X2);
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}
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[Test]
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public void RevX0X0()
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{
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// REV X0, X0
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ARegisters Registers = SingleOpcode(0xDAC00C00, X0: 0xAABBCCDDEEFF1100);
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Assert.AreEqual(0x0011FFEEDDCCBBAA, Registers.X0);
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}
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[Test]
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public void RevW1W1()
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{
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// REV W1, W1
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ARegisters Registers = SingleOpcode(0x5AC00821, X1: 0x12345678);
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Assert.AreEqual(0x78563412, Registers.X1);
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}
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}
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}
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