mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-20 07:38:42 +02:00
* Turn `MemoryOperand` into a struct * Remove `IntrinsicOperation` * Remove `PhiNode` * Remove `Node` * Turn `Operand` into a struct * Turn `Operation` into a struct * Clean up pool management methods * Add `Arena` allocator * Move `OperationHelper` to `Operation.Factory` * Move `OperandHelper` to `Operand.Factory` * Optimize `Operation` a bit * Fix `Arena` initialization * Rename `NativeList<T>` to `ArenaList<T>` * Reduce `Operand` size from 88 to 56 bytes * Reduce `Operation` size from 56 to 40 bytes * Add optimistic interning of Register & Constant operands * Optimize `RegisterUsage` pass a bit * Optimize `RemoveUnusedNodes` pass a bit Iterating in reverse-order allows killing dependency chains in a single pass. * Fix PPTC symbols * Optimize `BasicBlock` a bit Reduce allocations from `_successor` & `DominanceFrontiers` * Fix `Operation` resize * Make `Arena` expandable Change the arena allocator to be expandable by allocating in pages, with some of them being pooled. Currently 32 pages are pooled. An LRU removal mechanism should probably be added to it. Apparently MHR can allocate bitmaps large enough to exceed the 16MB limit for the type. * Move `Arena` & `ArenaList` to `Common` * Remove `ThreadStaticPool` & co * Add `PhiOperation` * Reduce `Operand` size from 56 from 48 bytes * Add linear-probing to `Operand` intern table * Optimize `HybridAllocator` a bit * Add `Allocators` class * Tune `ArenaAllocator` sizes * Add page removal mechanism to `ArenaAllocator` Remove pages which have not been used for more than 5s after each reset. I am on fence if this would be better using a Gen2 callback object like the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right now if a large translation happens, the pages will be freed only after a reset. This reset may not happen for a while because no new translation is hit, but the arena base sizes are rather small. * Fix `OOM` when allocating larger than page size in `ArenaAllocator` Tweak resizing mechanism for Operand.Uses and Assignemnts. * Optimize `Optimizer` a bit * Optimize `Operand.Add<T>/Remove<T>` a bit * Clean up `PreAllocator` * Fix phi insertion order Reduce codegen diffs. * Fix code alignment * Use new heuristics for degree of parallelism * Suppress warnings * Address gdkchan's feedback Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that `Operand.Value` should usually not be modified directly. * Add fast path to `ArenaAllocator` * Assembly for `ArenaAllocator.Allocate(ulong)`: .L0: mov rax, [rcx+0x18] lea r8, [rax+rdx] cmp r8, [rcx+0x10] ja short .L2 .L1: mov rdx, [rcx+8] add rax, [rdx+8] mov [rcx+0x18], r8 ret .L2: jmp ArenaAllocator.AllocateSlow(UInt64) A few variable/field had to be changed to ulong so that RyuJIT avoids emitting zero-extends. * Implement a new heuristic to free pooled pages. If an arena is used often, it is more likely that its pages will be needed, so the pages are kept for longer (e.g: during PPTC rebuild or burst sof compilations). If is not used often, then it is more likely that its pages will not be needed (e.g: after PPTC rebuild or bursts of compilations). * Address riperiperi's feedback * Use `EqualityComparer<T>` in `IntrusiveList<T>` Avoids a potential GC hole in `Equals(T, T)`.
184 lines
5.4 KiB
C#
184 lines
5.4 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitMemoryHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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public static void Adr(ArmEmitterContext context)
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{
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OpCodeAdr op = (OpCodeAdr)context.CurrOp;
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SetIntOrZR(context, op.Rd, Const(op.Address + (ulong)op.Immediate));
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}
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public static void Adrp(ArmEmitterContext context)
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{
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OpCodeAdr op = (OpCodeAdr)context.CurrOp;
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ulong address = (op.Address & ~0xfffUL) + ((ulong)op.Immediate << 12);
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SetIntOrZR(context, op.Rd, Const(address));
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}
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public static void Ldr(ArmEmitterContext context) => EmitLdr(context, signed: false);
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public static void Ldrs(ArmEmitterContext context) => EmitLdr(context, signed: true);
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private static void EmitLdr(ArmEmitterContext context, bool signed)
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{
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OpCodeMem op = (OpCodeMem)context.CurrOp;
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Operand address = GetAddress(context);
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if (signed && op.Extend64)
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{
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EmitLoadSx64(context, address, op.Rt, op.Size);
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}
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else if (signed)
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{
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EmitLoadSx32(context, address, op.Rt, op.Size);
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}
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else
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{
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EmitLoadZx(context, address, op.Rt, op.Size);
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}
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EmitWBackIfNeeded(context, address);
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}
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public static void Ldr_Literal(ArmEmitterContext context)
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{
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IOpCodeLit op = (IOpCodeLit)context.CurrOp;
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if (op.Prefetch)
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{
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return;
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}
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if (op.Signed)
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{
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EmitLoadSx64(context, Const(op.Immediate), op.Rt, op.Size);
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}
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else
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{
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EmitLoadZx(context, Const(op.Immediate), op.Rt, op.Size);
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}
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}
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public static void Ldp(ArmEmitterContext context)
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{
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OpCodeMemPair op = (OpCodeMemPair)context.CurrOp;
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void EmitLoad(int rt, Operand ldAddr)
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{
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if (op.Extend64)
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{
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EmitLoadSx64(context, ldAddr, rt, op.Size);
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}
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else
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{
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EmitLoadZx(context, ldAddr, rt, op.Size);
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}
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}
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Operand address = GetAddress(context);
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Operand address2 = GetAddress(context, 1L << op.Size);
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EmitLoad(op.Rt, address);
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EmitLoad(op.Rt2, address2);
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EmitWBackIfNeeded(context, address);
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}
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public static void Str(ArmEmitterContext context)
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{
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OpCodeMem op = (OpCodeMem)context.CurrOp;
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Operand address = GetAddress(context);
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InstEmitMemoryHelper.EmitStore(context, address, op.Rt, op.Size);
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EmitWBackIfNeeded(context, address);
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}
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public static void Stp(ArmEmitterContext context)
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{
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OpCodeMemPair op = (OpCodeMemPair)context.CurrOp;
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Operand address = GetAddress(context);
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Operand address2 = GetAddress(context, 1L << op.Size);
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InstEmitMemoryHelper.EmitStore(context, address, op.Rt, op.Size);
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InstEmitMemoryHelper.EmitStore(context, address2, op.Rt2, op.Size);
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EmitWBackIfNeeded(context, address);
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}
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private static Operand GetAddress(ArmEmitterContext context, long addend = 0)
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{
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Operand address = default;
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switch (context.CurrOp)
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{
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case OpCodeMemImm op:
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{
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address = context.Copy(GetIntOrSP(context, op.Rn));
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// Pre-indexing.
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if (!op.PostIdx)
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{
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address = context.Add(address, Const(op.Immediate + addend));
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}
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else if (addend != 0)
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{
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address = context.Add(address, Const(addend));
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}
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break;
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}
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case OpCodeMemReg op:
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{
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Operand n = GetIntOrSP(context, op.Rn);
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Operand m = GetExtendedM(context, op.Rm, op.IntType);
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if (op.Shift)
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{
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m = context.ShiftLeft(m, Const(op.Size));
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}
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address = context.Add(n, m);
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if (addend != 0)
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{
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address = context.Add(address, Const(addend));
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}
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break;
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}
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}
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return address;
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}
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private static void EmitWBackIfNeeded(ArmEmitterContext context, Operand address)
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{
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// Check whenever the current OpCode has post-indexed write back, if so write it.
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if (context.CurrOp is OpCodeMemImm op && op.WBack)
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{
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if (op.PostIdx)
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{
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address = context.Add(address, Const(op.Immediate));
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}
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SetIntOrSP(context, op.Rn, address);
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}
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}
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}
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} |