mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-20 15:48:43 +02:00
* Turn `MemoryOperand` into a struct * Remove `IntrinsicOperation` * Remove `PhiNode` * Remove `Node` * Turn `Operand` into a struct * Turn `Operation` into a struct * Clean up pool management methods * Add `Arena` allocator * Move `OperationHelper` to `Operation.Factory` * Move `OperandHelper` to `Operand.Factory` * Optimize `Operation` a bit * Fix `Arena` initialization * Rename `NativeList<T>` to `ArenaList<T>` * Reduce `Operand` size from 88 to 56 bytes * Reduce `Operation` size from 56 to 40 bytes * Add optimistic interning of Register & Constant operands * Optimize `RegisterUsage` pass a bit * Optimize `RemoveUnusedNodes` pass a bit Iterating in reverse-order allows killing dependency chains in a single pass. * Fix PPTC symbols * Optimize `BasicBlock` a bit Reduce allocations from `_successor` & `DominanceFrontiers` * Fix `Operation` resize * Make `Arena` expandable Change the arena allocator to be expandable by allocating in pages, with some of them being pooled. Currently 32 pages are pooled. An LRU removal mechanism should probably be added to it. Apparently MHR can allocate bitmaps large enough to exceed the 16MB limit for the type. * Move `Arena` & `ArenaList` to `Common` * Remove `ThreadStaticPool` & co * Add `PhiOperation` * Reduce `Operand` size from 56 from 48 bytes * Add linear-probing to `Operand` intern table * Optimize `HybridAllocator` a bit * Add `Allocators` class * Tune `ArenaAllocator` sizes * Add page removal mechanism to `ArenaAllocator` Remove pages which have not been used for more than 5s after each reset. I am on fence if this would be better using a Gen2 callback object like the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right now if a large translation happens, the pages will be freed only after a reset. This reset may not happen for a while because no new translation is hit, but the arena base sizes are rather small. * Fix `OOM` when allocating larger than page size in `ArenaAllocator` Tweak resizing mechanism for Operand.Uses and Assignemnts. * Optimize `Optimizer` a bit * Optimize `Operand.Add<T>/Remove<T>` a bit * Clean up `PreAllocator` * Fix phi insertion order Reduce codegen diffs. * Fix code alignment * Use new heuristics for degree of parallelism * Suppress warnings * Address gdkchan's feedback Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that `Operand.Value` should usually not be modified directly. * Add fast path to `ArenaAllocator` * Assembly for `ArenaAllocator.Allocate(ulong)`: .L0: mov rax, [rcx+0x18] lea r8, [rax+rdx] cmp r8, [rcx+0x10] ja short .L2 .L1: mov rdx, [rcx+8] add rax, [rdx+8] mov [rcx+0x18], r8 ret .L2: jmp ArenaAllocator.AllocateSlow(UInt64) A few variable/field had to be changed to ulong so that RyuJIT avoids emitting zero-extends. * Implement a new heuristic to free pooled pages. If an arena is used often, it is more likely that its pages will be needed, so the pages are kept for longer (e.g: during PPTC rebuild or burst sof compilations). If is not used often, then it is more likely that its pages will not be needed (e.g: after PPTC rebuild or bursts of compilations). * Address riperiperi's feedback * Use `EqualityComparer<T>` in `IntrusiveList<T>` Avoids a potential GC hole in `Equals(T, T)`.
175 lines
6.5 KiB
C#
175 lines
6.5 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitMemoryExHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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[Flags]
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private enum AccessType
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{
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None = 0,
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Ordered = 1,
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Exclusive = 2,
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OrderedEx = Ordered | Exclusive
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}
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public static void Clrex(ArmEmitterContext context)
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{
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EmitClearExclusive(context);
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}
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public static void Dmb(ArmEmitterContext context) => EmitBarrier(context);
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public static void Dsb(ArmEmitterContext context) => EmitBarrier(context);
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public static void Ldar(ArmEmitterContext context) => EmitLdr(context, AccessType.Ordered);
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public static void Ldaxr(ArmEmitterContext context) => EmitLdr(context, AccessType.OrderedEx);
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public static void Ldxr(ArmEmitterContext context) => EmitLdr(context, AccessType.Exclusive);
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public static void Ldxp(ArmEmitterContext context) => EmitLdp(context, AccessType.Exclusive);
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public static void Ldaxp(ArmEmitterContext context) => EmitLdp(context, AccessType.OrderedEx);
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private static void EmitLdr(ArmEmitterContext context, AccessType accType)
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{
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EmitLoadEx(context, accType, pair: false);
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}
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private static void EmitLdp(ArmEmitterContext context, AccessType accType)
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{
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EmitLoadEx(context, accType, pair: true);
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}
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private static void EmitLoadEx(ArmEmitterContext context, AccessType accType, bool pair)
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{
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OpCodeMemEx op = (OpCodeMemEx)context.CurrOp;
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bool ordered = (accType & AccessType.Ordered) != 0;
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bool exclusive = (accType & AccessType.Exclusive) != 0;
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if (ordered)
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{
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EmitBarrier(context);
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}
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Operand address = context.Copy(GetIntOrSP(context, op.Rn));
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if (pair)
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{
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// Exclusive loads should be atomic. For pairwise loads, we need to
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// read all the data at once. For a 32-bits pairwise load, we do a
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// simple 64-bits load, for a 128-bits load, we need to call a special
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// method to read 128-bits atomically.
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if (op.Size == 2)
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{
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Operand value = EmitLoadExclusive(context, address, exclusive, 3);
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Operand valueLow = context.ConvertI64ToI32(value);
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valueLow = context.ZeroExtend32(OperandType.I64, valueLow);
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Operand valueHigh = context.ShiftRightUI(value, Const(32));
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SetIntOrZR(context, op.Rt, valueLow);
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SetIntOrZR(context, op.Rt2, valueHigh);
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}
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else if (op.Size == 3)
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{
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Operand value = EmitLoadExclusive(context, address, exclusive, 4);
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Operand valueLow = context.VectorExtract(OperandType.I64, value, 0);
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Operand valueHigh = context.VectorExtract(OperandType.I64, value, 1);
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SetIntOrZR(context, op.Rt, valueLow);
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SetIntOrZR(context, op.Rt2, valueHigh);
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}
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else
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{
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throw new InvalidOperationException($"Invalid load size of {1 << op.Size} bytes.");
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}
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}
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else
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{
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// 8, 16, 32 or 64-bits (non-pairwise) load.
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Operand value = EmitLoadExclusive(context, address, exclusive, op.Size);
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SetIntOrZR(context, op.Rt, value);
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}
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}
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public static void Prfm(ArmEmitterContext context)
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{
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// Memory Prefetch, execute as no-op.
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}
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public static void Stlr(ArmEmitterContext context) => EmitStr(context, AccessType.Ordered);
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public static void Stlxr(ArmEmitterContext context) => EmitStr(context, AccessType.OrderedEx);
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public static void Stxr(ArmEmitterContext context) => EmitStr(context, AccessType.Exclusive);
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public static void Stxp(ArmEmitterContext context) => EmitStp(context, AccessType.Exclusive);
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public static void Stlxp(ArmEmitterContext context) => EmitStp(context, AccessType.OrderedEx);
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private static void EmitStr(ArmEmitterContext context, AccessType accType)
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{
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EmitStoreEx(context, accType, pair: false);
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}
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private static void EmitStp(ArmEmitterContext context, AccessType accType)
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{
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EmitStoreEx(context, accType, pair: true);
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}
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private static void EmitStoreEx(ArmEmitterContext context, AccessType accType, bool pair)
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{
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OpCodeMemEx op = (OpCodeMemEx)context.CurrOp;
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bool ordered = (accType & AccessType.Ordered) != 0;
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bool exclusive = (accType & AccessType.Exclusive) != 0;
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if (ordered)
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{
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EmitBarrier(context);
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}
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Operand address = context.Copy(GetIntOrSP(context, op.Rn));
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Operand t = GetIntOrZR(context, op.Rt);
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if (pair)
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{
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Debug.Assert(op.Size == 2 || op.Size == 3, "Invalid size for pairwise store.");
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Operand t2 = GetIntOrZR(context, op.Rt2);
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Operand value;
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if (op.Size == 2)
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{
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value = context.BitwiseOr(t, context.ShiftLeft(t2, Const(32)));
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}
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else /* if (op.Size == 3) */
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{
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value = context.VectorInsert(context.VectorZero(), t, 0);
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value = context.VectorInsert(value, t2, 1);
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}
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EmitStoreExclusive(context, address, value, exclusive, op.Size + 1, op.Rs, a32: false);
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}
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else
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{
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EmitStoreExclusive(context, address, t, exclusive, op.Size, op.Rs, a32: false);
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}
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}
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private static void EmitBarrier(ArmEmitterContext context)
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{
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// Note: This barrier is most likely not necessary, and probably
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// doesn't make any difference since we need to do a ton of stuff
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// (software MMU emulation) to read or write anything anyway.
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}
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}
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} |