mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-09-11 10:18:52 +02:00
* Turn `MemoryOperand` into a struct * Remove `IntrinsicOperation` * Remove `PhiNode` * Remove `Node` * Turn `Operand` into a struct * Turn `Operation` into a struct * Clean up pool management methods * Add `Arena` allocator * Move `OperationHelper` to `Operation.Factory` * Move `OperandHelper` to `Operand.Factory` * Optimize `Operation` a bit * Fix `Arena` initialization * Rename `NativeList<T>` to `ArenaList<T>` * Reduce `Operand` size from 88 to 56 bytes * Reduce `Operation` size from 56 to 40 bytes * Add optimistic interning of Register & Constant operands * Optimize `RegisterUsage` pass a bit * Optimize `RemoveUnusedNodes` pass a bit Iterating in reverse-order allows killing dependency chains in a single pass. * Fix PPTC symbols * Optimize `BasicBlock` a bit Reduce allocations from `_successor` & `DominanceFrontiers` * Fix `Operation` resize * Make `Arena` expandable Change the arena allocator to be expandable by allocating in pages, with some of them being pooled. Currently 32 pages are pooled. An LRU removal mechanism should probably be added to it. Apparently MHR can allocate bitmaps large enough to exceed the 16MB limit for the type. * Move `Arena` & `ArenaList` to `Common` * Remove `ThreadStaticPool` & co * Add `PhiOperation` * Reduce `Operand` size from 56 from 48 bytes * Add linear-probing to `Operand` intern table * Optimize `HybridAllocator` a bit * Add `Allocators` class * Tune `ArenaAllocator` sizes * Add page removal mechanism to `ArenaAllocator` Remove pages which have not been used for more than 5s after each reset. I am on fence if this would be better using a Gen2 callback object like the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right now if a large translation happens, the pages will be freed only after a reset. This reset may not happen for a while because no new translation is hit, but the arena base sizes are rather small. * Fix `OOM` when allocating larger than page size in `ArenaAllocator` Tweak resizing mechanism for Operand.Uses and Assignemnts. * Optimize `Optimizer` a bit * Optimize `Operand.Add<T>/Remove<T>` a bit * Clean up `PreAllocator` * Fix phi insertion order Reduce codegen diffs. * Fix code alignment * Use new heuristics for degree of parallelism * Suppress warnings * Address gdkchan's feedback Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that `Operand.Value` should usually not be modified directly. * Add fast path to `ArenaAllocator` * Assembly for `ArenaAllocator.Allocate(ulong)`: .L0: mov rax, [rcx+0x18] lea r8, [rax+rdx] cmp r8, [rcx+0x10] ja short .L2 .L1: mov rdx, [rcx+8] add rax, [rdx+8] mov [rcx+0x18], r8 ret .L2: jmp ArenaAllocator.AllocateSlow(UInt64) A few variable/field had to be changed to ulong so that RyuJIT avoids emitting zero-extends. * Implement a new heuristic to free pooled pages. If an arena is used often, it is more likely that its pages will be needed, so the pages are kept for longer (e.g: during PPTC rebuild or burst sof compilations). If is not used often, then it is more likely that its pages will not be needed (e.g: after PPTC rebuild or bursts of compilations). * Address riperiperi's feedback * Use `EqualityComparer<T>` in `IntrusiveList<T>` Avoids a potential GC hole in `Equals(T, T)`.
227 lines
8.1 KiB
C#
227 lines
8.1 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitMemoryExHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void Clrex(ArmEmitterContext context)
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{
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EmitClearExclusive(context);
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}
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public static void Dmb(ArmEmitterContext context) => EmitBarrier(context);
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public static void Dsb(ArmEmitterContext context) => EmitBarrier(context);
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public static void Ldrex(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, WordSizeLog2, AccessType.LoadZx | AccessType.Exclusive);
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}
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public static void Ldrexb(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, ByteSizeLog2, AccessType.LoadZx | AccessType.Exclusive);
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}
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public static void Ldrexd(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, DWordSizeLog2, AccessType.LoadZx | AccessType.Exclusive);
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}
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public static void Ldrexh(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, HWordSizeLog2, AccessType.LoadZx | AccessType.Exclusive);
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}
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public static void Lda(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, WordSizeLog2, AccessType.LoadZx | AccessType.Ordered);
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}
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public static void Ldab(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, ByteSizeLog2, AccessType.LoadZx | AccessType.Ordered);
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}
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public static void Ldaex(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, WordSizeLog2, AccessType.LoadZx | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Ldaexb(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, ByteSizeLog2, AccessType.LoadZx | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Ldaexd(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, DWordSizeLog2, AccessType.LoadZx | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Ldaexh(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, HWordSizeLog2, AccessType.LoadZx | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Ldah(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, HWordSizeLog2, AccessType.LoadZx | AccessType.Ordered);
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}
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// Stores.
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public static void Strex(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, WordSizeLog2, AccessType.Store | AccessType.Exclusive);
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}
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public static void Strexb(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, ByteSizeLog2, AccessType.Store | AccessType.Exclusive);
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}
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public static void Strexd(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, DWordSizeLog2, AccessType.Store | AccessType.Exclusive);
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}
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public static void Strexh(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, HWordSizeLog2, AccessType.Store | AccessType.Exclusive);
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}
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public static void Stl(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, WordSizeLog2, AccessType.Store | AccessType.Ordered);
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}
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public static void Stlb(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, ByteSizeLog2, AccessType.Store | AccessType.Ordered);
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}
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public static void Stlex(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, WordSizeLog2, AccessType.Store | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Stlexb(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, ByteSizeLog2, AccessType.Store | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Stlexd(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, DWordSizeLog2, AccessType.Store | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Stlexh(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, HWordSizeLog2, AccessType.Store | AccessType.Exclusive | AccessType.Ordered);
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}
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public static void Stlh(ArmEmitterContext context)
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{
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EmitExLoadOrStore(context, HWordSizeLog2, AccessType.Store | AccessType.Ordered);
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}
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private static void EmitExLoadOrStore(ArmEmitterContext context, int size, AccessType accType)
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{
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IOpCode32MemEx op = (IOpCode32MemEx)context.CurrOp;
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Operand address = context.Copy(GetIntA32(context, op.Rn));
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var exclusive = (accType & AccessType.Exclusive) != 0;
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var ordered = (accType & AccessType.Ordered) != 0;
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if (ordered)
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{
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EmitBarrier(context);
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}
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if ((accType & AccessType.Load) != 0)
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{
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if (size == DWordSizeLog2)
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{
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// Keep loads atomic - make the call to get the whole region and then decompose it into parts
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// for the registers.
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Operand value = EmitLoadExclusive(context, address, exclusive, size);
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Operand valueLow = context.ConvertI64ToI32(value);
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valueLow = context.ZeroExtend32(OperandType.I64, valueLow);
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Operand valueHigh = context.ShiftRightUI(value, Const(32));
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Operand lblBigEndian = Label();
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Operand lblEnd = Label();
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context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
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SetIntA32(context, op.Rt, valueLow);
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SetIntA32(context, op.Rt | 1, valueHigh);
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context.Branch(lblEnd);
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context.MarkLabel(lblBigEndian);
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SetIntA32(context, op.Rt | 1, valueLow);
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SetIntA32(context, op.Rt, valueHigh);
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context.MarkLabel(lblEnd);
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}
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else
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{
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SetIntA32(context, op.Rt, EmitLoadExclusive(context, address, exclusive, size));
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}
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}
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else
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{
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if (size == DWordSizeLog2)
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{
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// Split the result into 2 words (based on endianness)
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Operand lo = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt));
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Operand hi = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt | 1));
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Operand lblBigEndian = Label();
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Operand lblEnd = Label();
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context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
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Operand leResult = context.BitwiseOr(lo, context.ShiftLeft(hi, Const(32)));
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EmitStoreExclusive(context, address, leResult, exclusive, size, op.Rd, a32: true);
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context.Branch(lblEnd);
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context.MarkLabel(lblBigEndian);
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Operand beResult = context.BitwiseOr(hi, context.ShiftLeft(lo, Const(32)));
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EmitStoreExclusive(context, address, beResult, exclusive, size, op.Rd, a32: true);
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context.MarkLabel(lblEnd);
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}
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else
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{
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Operand value = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt));
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EmitStoreExclusive(context, address, value, exclusive, size, op.Rd, a32: true);
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}
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}
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}
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private static void EmitBarrier(ArmEmitterContext context)
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{
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// Note: This barrier is most likely not necessary, and probably
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// doesn't make any difference since we need to do a ton of stuff
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// (software MMU emulation) to read or write anything anyway.
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}
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}
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}
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