mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-20 07:38:42 +02:00
* Turn `MemoryOperand` into a struct * Remove `IntrinsicOperation` * Remove `PhiNode` * Remove `Node` * Turn `Operand` into a struct * Turn `Operation` into a struct * Clean up pool management methods * Add `Arena` allocator * Move `OperationHelper` to `Operation.Factory` * Move `OperandHelper` to `Operand.Factory` * Optimize `Operation` a bit * Fix `Arena` initialization * Rename `NativeList<T>` to `ArenaList<T>` * Reduce `Operand` size from 88 to 56 bytes * Reduce `Operation` size from 56 to 40 bytes * Add optimistic interning of Register & Constant operands * Optimize `RegisterUsage` pass a bit * Optimize `RemoveUnusedNodes` pass a bit Iterating in reverse-order allows killing dependency chains in a single pass. * Fix PPTC symbols * Optimize `BasicBlock` a bit Reduce allocations from `_successor` & `DominanceFrontiers` * Fix `Operation` resize * Make `Arena` expandable Change the arena allocator to be expandable by allocating in pages, with some of them being pooled. Currently 32 pages are pooled. An LRU removal mechanism should probably be added to it. Apparently MHR can allocate bitmaps large enough to exceed the 16MB limit for the type. * Move `Arena` & `ArenaList` to `Common` * Remove `ThreadStaticPool` & co * Add `PhiOperation` * Reduce `Operand` size from 56 from 48 bytes * Add linear-probing to `Operand` intern table * Optimize `HybridAllocator` a bit * Add `Allocators` class * Tune `ArenaAllocator` sizes * Add page removal mechanism to `ArenaAllocator` Remove pages which have not been used for more than 5s after each reset. I am on fence if this would be better using a Gen2 callback object like the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right now if a large translation happens, the pages will be freed only after a reset. This reset may not happen for a while because no new translation is hit, but the arena base sizes are rather small. * Fix `OOM` when allocating larger than page size in `ArenaAllocator` Tweak resizing mechanism for Operand.Uses and Assignemnts. * Optimize `Optimizer` a bit * Optimize `Operand.Add<T>/Remove<T>` a bit * Clean up `PreAllocator` * Fix phi insertion order Reduce codegen diffs. * Fix code alignment * Use new heuristics for degree of parallelism * Suppress warnings * Address gdkchan's feedback Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that `Operand.Value` should usually not be modified directly. * Add fast path to `ArenaAllocator` * Assembly for `ArenaAllocator.Allocate(ulong)`: .L0: mov rax, [rcx+0x18] lea r8, [rax+rdx] cmp r8, [rcx+0x10] ja short .L2 .L1: mov rdx, [rcx+8] add rax, [rdx+8] mov [rcx+0x18], r8 ret .L2: jmp ArenaAllocator.AllocateSlow(UInt64) A few variable/field had to be changed to ulong so that RyuJIT avoids emitting zero-extends. * Implement a new heuristic to free pooled pages. If an arena is used often, it is more likely that its pages will be needed, so the pages are kept for longer (e.g: during PPTC rebuild or burst sof compilations). If is not used often, then it is more likely that its pages will not be needed (e.g: after PPTC rebuild or bursts of compilations). * Address riperiperi's feedback * Use `EqualityComparer<T>` in `IntrusiveList<T>` Avoids a potential GC hole in `Equals(T, T)`.
382 lines
14 KiB
C#
382 lines
14 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using System;
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using System.Numerics;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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using static ARMeilleure.IntermediateRepresentation.Operation.Factory;
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namespace ARMeilleure.Translation
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{
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static class RegisterUsage
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{
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private const int RegsCount = 32;
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private const int RegsMask = RegsCount - 1;
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private struct RegisterMask : IEquatable<RegisterMask>
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{
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public long IntMask => Mask.GetElement(0);
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public long VecMask => Mask.GetElement(1);
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public Vector128<long> Mask { get; }
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public RegisterMask(Vector128<long> mask)
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{
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Mask = mask;
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}
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public RegisterMask(long intMask, long vecMask)
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{
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Mask = Vector128.Create(intMask, vecMask);
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}
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public static RegisterMask operator &(RegisterMask x, RegisterMask y)
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{
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if (Sse2.IsSupported)
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{
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return new RegisterMask(Sse2.And(x.Mask, y.Mask));
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}
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return new RegisterMask(x.IntMask & y.IntMask, x.VecMask & y.VecMask);
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}
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public static RegisterMask operator |(RegisterMask x, RegisterMask y)
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{
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if (Sse2.IsSupported)
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{
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return new RegisterMask(Sse2.Or(x.Mask, y.Mask));
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}
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return new RegisterMask(x.IntMask | y.IntMask, x.VecMask | y.VecMask);
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}
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public static RegisterMask operator ~(RegisterMask x)
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{
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if (Sse2.IsSupported)
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{
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return new RegisterMask(Sse2.AndNot(x.Mask, Vector128<long>.AllBitsSet));
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}
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return new RegisterMask(~x.IntMask, ~x.VecMask);
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}
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public static bool operator ==(RegisterMask x, RegisterMask y)
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{
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return x.Equals(y);
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}
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public static bool operator !=(RegisterMask x, RegisterMask y)
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{
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return !x.Equals(y);
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}
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public override bool Equals(object obj)
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{
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return obj is RegisterMask regMask && Equals(regMask);
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}
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public bool Equals(RegisterMask other)
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{
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return Mask.Equals(other.Mask);
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}
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public override int GetHashCode()
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{
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return Mask.GetHashCode();
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}
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}
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public static void RunPass(ControlFlowGraph cfg, ExecutionMode mode)
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{
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// Compute local register inputs and outputs used inside blocks.
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RegisterMask[] localInputs = new RegisterMask[cfg.Blocks.Count];
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RegisterMask[] localOutputs = new RegisterMask[cfg.Blocks.Count];
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for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext)
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{
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for (Operation node = block.Operations.First; node != default; node = node.ListNext)
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{
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for (int index = 0; index < node.SourcesCount; index++)
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{
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Operand source = node.GetSource(index);
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if (source.Kind == OperandKind.Register)
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{
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Register register = source.GetRegister();
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localInputs[block.Index] |= GetMask(register) & ~localOutputs[block.Index];
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}
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}
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if (node.Destination != default && node.Destination.Kind == OperandKind.Register)
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{
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localOutputs[block.Index] |= GetMask(node.Destination.GetRegister());
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}
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}
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}
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// Compute global register inputs and outputs used across blocks.
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RegisterMask[] globalCmnOutputs = new RegisterMask[cfg.Blocks.Count];
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RegisterMask[] globalInputs = new RegisterMask[cfg.Blocks.Count];
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RegisterMask[] globalOutputs = new RegisterMask[cfg.Blocks.Count];
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bool modified;
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bool firstPass = true;
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do
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{
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modified = false;
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// Compute register outputs.
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for (int index = cfg.PostOrderBlocks.Length - 1; index >= 0; index--)
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{
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BasicBlock block = cfg.PostOrderBlocks[index];
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if (block.Predecessors.Count != 0 && !HasContextLoad(block))
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{
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BasicBlock predecessor = block.Predecessors[0];
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RegisterMask cmnOutputs = localOutputs[predecessor.Index] | globalCmnOutputs[predecessor.Index];
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RegisterMask outputs = globalOutputs[predecessor.Index];
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for (int pIndex = 1; pIndex < block.Predecessors.Count; pIndex++)
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{
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predecessor = block.Predecessors[pIndex];
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cmnOutputs &= localOutputs[predecessor.Index] | globalCmnOutputs[predecessor.Index];
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outputs |= globalOutputs[predecessor.Index];
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}
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globalInputs[block.Index] |= outputs & ~cmnOutputs;
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if (!firstPass)
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{
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cmnOutputs &= globalCmnOutputs[block.Index];
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}
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modified |= Exchange(globalCmnOutputs, block.Index, cmnOutputs);
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outputs |= localOutputs[block.Index];
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modified |= Exchange(globalOutputs, block.Index, globalOutputs[block.Index] | outputs);
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}
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else
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{
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modified |= Exchange(globalOutputs, block.Index, localOutputs[block.Index]);
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}
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}
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// Compute register inputs.
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for (int index = 0; index < cfg.PostOrderBlocks.Length; index++)
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{
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BasicBlock block = cfg.PostOrderBlocks[index];
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RegisterMask inputs = localInputs[block.Index];
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for (int i = 0; i < block.SuccessorsCount; i++)
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{
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inputs |= globalInputs[block.GetSuccessor(i).Index];
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}
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inputs &= ~globalCmnOutputs[block.Index];
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modified |= Exchange(globalInputs, block.Index, globalInputs[block.Index] | inputs);
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}
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firstPass = false;
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}
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while (modified);
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// Insert load and store context instructions where needed.
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for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext)
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{
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bool hasContextLoad = HasContextLoad(block);
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if (hasContextLoad)
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{
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block.Operations.Remove(block.Operations.First);
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}
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Operand arg = default;
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// The only block without any predecessor should be the entry block.
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// It always needs a context load as it is the first block to run.
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if (block.Predecessors.Count == 0 || hasContextLoad)
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{
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arg = Local(OperandType.I64);
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Operation loadArg = block.Operations.AddFirst(Operation(Instruction.LoadArgument, arg, Const(0)));
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LoadLocals(block, globalInputs[block.Index].VecMask, RegisterType.Vector, mode, loadArg, arg);
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LoadLocals(block, globalInputs[block.Index].IntMask, RegisterType.Integer, mode, loadArg, arg);
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}
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bool hasContextStore = HasContextStore(block);
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if (hasContextStore)
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{
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block.Operations.Remove(block.Operations.Last);
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}
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if (EndsWithReturn(block) || hasContextStore)
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{
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if (arg == default)
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{
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arg = Local(OperandType.I64);
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block.Append(Operation(Instruction.LoadArgument, arg, Const(0)));
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}
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StoreLocals(block, globalOutputs[block.Index].IntMask, RegisterType.Integer, mode, arg);
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StoreLocals(block, globalOutputs[block.Index].VecMask, RegisterType.Vector, mode, arg);
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}
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}
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}
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private static bool HasContextLoad(BasicBlock block)
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{
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return StartsWith(block, Instruction.LoadFromContext) && block.Operations.First.SourcesCount == 0;
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}
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private static bool HasContextStore(BasicBlock block)
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{
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return EndsWith(block, Instruction.StoreToContext) && block.Operations.Last.SourcesCount == 0;
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}
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private static bool StartsWith(BasicBlock block, Instruction inst)
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{
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if (block.Operations.Count > 0)
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{
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Operation first = block.Operations.First;
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return first != default && first.Instruction == inst;
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}
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return false;
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}
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private static bool EndsWith(BasicBlock block, Instruction inst)
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{
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if (block.Operations.Count > 0)
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{
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Operation last = block.Operations.Last;
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return last != default && last.Instruction == inst;
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}
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return false;
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}
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private static RegisterMask GetMask(Register register)
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{
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long intMask = 0;
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long vecMask = 0;
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switch (register.Type)
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{
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case RegisterType.Flag: intMask = (1L << RegsCount) << register.Index; break;
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case RegisterType.Integer: intMask = 1L << register.Index; break;
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case RegisterType.FpFlag: vecMask = (1L << RegsCount) << register.Index; break;
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case RegisterType.Vector: vecMask = 1L << register.Index; break;
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}
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return new RegisterMask(intMask, vecMask);
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}
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private static bool Exchange(RegisterMask[] masks, int blkIndex, RegisterMask value)
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{
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ref RegisterMask curValue = ref masks[blkIndex];
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bool changed = curValue != value;
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curValue = value;
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return changed;
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}
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private static void LoadLocals(
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BasicBlock block,
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long inputs,
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RegisterType baseType,
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ExecutionMode mode,
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Operation loadArg,
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Operand arg)
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{
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while (inputs != 0)
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{
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int bit = 63 - BitOperations.LeadingZeroCount((ulong)inputs);
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Operand dest = GetRegFromBit(bit, baseType, mode);
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Operand offset = Const((long)NativeContext.GetRegisterOffset(dest.GetRegister()));
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Operand addr = Local(OperandType.I64);
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block.Operations.AddAfter(loadArg, Operation(Instruction.Load, dest, addr));
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block.Operations.AddAfter(loadArg, Operation(Instruction.Add, addr, arg, offset));
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inputs &= ~(1L << bit);
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}
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}
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private static void StoreLocals(
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BasicBlock block,
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long outputs,
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RegisterType baseType,
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ExecutionMode mode,
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Operand arg)
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{
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while (outputs != 0)
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{
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int bit = BitOperations.TrailingZeroCount(outputs);
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Operand source = GetRegFromBit(bit, baseType, mode);
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Operand offset = Const((long)NativeContext.GetRegisterOffset(source.GetRegister()));
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Operand addr = Local(OperandType.I64);
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block.Append(Operation(Instruction.Add, addr, arg, offset));
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block.Append(Operation(Instruction.Store, default, addr, source));
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outputs &= ~(1L << bit);
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}
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}
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private static Operand GetRegFromBit(int bit, RegisterType baseType, ExecutionMode mode)
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{
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if (bit < RegsCount)
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{
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return Register(bit, baseType, GetOperandType(baseType, mode));
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}
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else if (baseType == RegisterType.Integer)
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{
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return Register(bit & RegsMask, RegisterType.Flag, OperandType.I32);
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}
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else if (baseType == RegisterType.Vector)
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{
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return Register(bit & RegsMask, RegisterType.FpFlag, OperandType.I32);
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}
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else
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{
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throw new ArgumentOutOfRangeException(nameof(bit));
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}
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}
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private static OperandType GetOperandType(RegisterType type, ExecutionMode mode)
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{
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switch (type)
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{
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case RegisterType.Flag: return OperandType.I32;
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case RegisterType.FpFlag: return OperandType.I32;
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case RegisterType.Integer: return (mode == ExecutionMode.Aarch64) ? OperandType.I64 : OperandType.I32;
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case RegisterType.Vector: return OperandType.V128;
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}
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throw new ArgumentException($"Invalid register type \"{type}\".");
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}
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private static bool EndsWithReturn(BasicBlock block)
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{
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Operation last = block.Operations.Last;
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return last != default && last.Instruction == Instruction.Return;
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}
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}
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} |