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https://github.com/Ryujinx/Ryujinx.git
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* Turn `MemoryOperand` into a struct * Remove `IntrinsicOperation` * Remove `PhiNode` * Remove `Node` * Turn `Operand` into a struct * Turn `Operation` into a struct * Clean up pool management methods * Add `Arena` allocator * Move `OperationHelper` to `Operation.Factory` * Move `OperandHelper` to `Operand.Factory` * Optimize `Operation` a bit * Fix `Arena` initialization * Rename `NativeList<T>` to `ArenaList<T>` * Reduce `Operand` size from 88 to 56 bytes * Reduce `Operation` size from 56 to 40 bytes * Add optimistic interning of Register & Constant operands * Optimize `RegisterUsage` pass a bit * Optimize `RemoveUnusedNodes` pass a bit Iterating in reverse-order allows killing dependency chains in a single pass. * Fix PPTC symbols * Optimize `BasicBlock` a bit Reduce allocations from `_successor` & `DominanceFrontiers` * Fix `Operation` resize * Make `Arena` expandable Change the arena allocator to be expandable by allocating in pages, with some of them being pooled. Currently 32 pages are pooled. An LRU removal mechanism should probably be added to it. Apparently MHR can allocate bitmaps large enough to exceed the 16MB limit for the type. * Move `Arena` & `ArenaList` to `Common` * Remove `ThreadStaticPool` & co * Add `PhiOperation` * Reduce `Operand` size from 56 from 48 bytes * Add linear-probing to `Operand` intern table * Optimize `HybridAllocator` a bit * Add `Allocators` class * Tune `ArenaAllocator` sizes * Add page removal mechanism to `ArenaAllocator` Remove pages which have not been used for more than 5s after each reset. I am on fence if this would be better using a Gen2 callback object like the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right now if a large translation happens, the pages will be freed only after a reset. This reset may not happen for a while because no new translation is hit, but the arena base sizes are rather small. * Fix `OOM` when allocating larger than page size in `ArenaAllocator` Tweak resizing mechanism for Operand.Uses and Assignemnts. * Optimize `Optimizer` a bit * Optimize `Operand.Add<T>/Remove<T>` a bit * Clean up `PreAllocator` * Fix phi insertion order Reduce codegen diffs. * Fix code alignment * Use new heuristics for degree of parallelism * Suppress warnings * Address gdkchan's feedback Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that `Operand.Value` should usually not be modified directly. * Add fast path to `ArenaAllocator` * Assembly for `ArenaAllocator.Allocate(ulong)`: .L0: mov rax, [rcx+0x18] lea r8, [rax+rdx] cmp r8, [rcx+0x10] ja short .L2 .L1: mov rdx, [rcx+8] add rax, [rdx+8] mov [rcx+0x18], r8 ret .L2: jmp ArenaAllocator.AllocateSlow(UInt64) A few variable/field had to be changed to ulong so that RyuJIT avoids emitting zero-extends. * Implement a new heuristic to free pooled pages. If an arena is used often, it is more likely that its pages will be needed, so the pages are kept for longer (e.g: during PPTC rebuild or burst sof compilations). If is not used often, then it is more likely that its pages will not be needed (e.g: after PPTC rebuild or bursts of compilations). * Address riperiperi's feedback * Use `EqualityComparer<T>` in `IntrusiveList<T>` Avoids a potential GC hole in `Equals(T, T)`.
175 lines
6.5 KiB
C#
175 lines
6.5 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static class InstEmitMemoryExHelper
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{
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private const int ErgSizeLog2 = 4;
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public static Operand EmitLoadExclusive(ArmEmitterContext context, Operand address, bool exclusive, int size)
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{
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if (exclusive)
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{
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Operand value;
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if (size == 4)
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{
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// Only 128-bit CAS is guaranteed to have a atomic load.
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Operand physAddr = InstEmitMemoryHelper.EmitPtPointerLoad(context, address, default, write: false, 4);
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Operand zero = context.VectorZero();
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value = context.CompareAndSwap(physAddr, zero, zero);
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}
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else
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{
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value = InstEmitMemoryHelper.EmitReadIntAligned(context, address, size);
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}
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Operand arg0 = context.LoadArgument(OperandType.I64, 0);
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Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset()));
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Operand exValuePtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveValueOffset()));
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context.Store(exAddrPtr, context.BitwiseAnd(address, Const(address.Type, GetExclusiveAddressMask())));
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// Make sure the unused higher bits of the value are cleared.
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if (size < 3)
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{
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context.Store(exValuePtr, Const(0UL));
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}
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if (size < 4)
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{
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context.Store(context.Add(exValuePtr, Const(exValuePtr.Type, 8L)), Const(0UL));
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}
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// Store the new exclusive value.
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context.Store(exValuePtr, value);
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return value;
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}
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else
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{
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return InstEmitMemoryHelper.EmitReadIntAligned(context, address, size);
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}
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}
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public static void EmitStoreExclusive(
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ArmEmitterContext context,
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Operand address,
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Operand value,
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bool exclusive,
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int size,
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int rs,
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bool a32)
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{
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if (size < 3)
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{
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value = context.ConvertI64ToI32(value);
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}
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if (exclusive)
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{
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// We overwrite one of the register (Rs),
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// keep a copy of the values to ensure we are working with the correct values.
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address = context.Copy(address);
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value = context.Copy(value);
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void SetRs(Operand value)
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{
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if (a32)
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{
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SetIntA32(context, rs, value);
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}
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else
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{
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SetIntOrZR(context, rs, value);
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}
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}
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Operand arg0 = context.LoadArgument(OperandType.I64, 0);
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Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset()));
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Operand exAddr = context.Load(address.Type, exAddrPtr);
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// STEP 1: Check if we have exclusive access to this memory region. If not, fail and skip store.
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Operand maskedAddress = context.BitwiseAnd(address, Const(address.Type, GetExclusiveAddressMask()));
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Operand exFailed = context.ICompareNotEqual(exAddr, maskedAddress);
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Operand lblExit = Label();
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SetRs(Const(1));
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context.BranchIfTrue(lblExit, exFailed);
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// STEP 2: We have exclusive access and the address is valid, attempt the store using CAS.
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Operand physAddr = InstEmitMemoryHelper.EmitPtPointerLoad(context, address, default, write: true, size);
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Operand exValuePtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveValueOffset()));
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Operand exValue = size switch
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{
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0 => context.Load8(exValuePtr),
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1 => context.Load16(exValuePtr),
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2 => context.Load(OperandType.I32, exValuePtr),
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3 => context.Load(OperandType.I64, exValuePtr),
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_ => context.Load(OperandType.V128, exValuePtr)
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};
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Operand currValue = size switch
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{
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0 => context.CompareAndSwap8(physAddr, exValue, value),
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1 => context.CompareAndSwap16(physAddr, exValue, value),
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_ => context.CompareAndSwap(physAddr, exValue, value)
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};
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// STEP 3: Check if we succeeded by comparing expected and in-memory values.
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Operand storeFailed;
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if (size == 4)
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{
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Operand currValueLow = context.VectorExtract(OperandType.I64, currValue, 0);
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Operand currValueHigh = context.VectorExtract(OperandType.I64, currValue, 1);
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Operand exValueLow = context.VectorExtract(OperandType.I64, exValue, 0);
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Operand exValueHigh = context.VectorExtract(OperandType.I64, exValue, 1);
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storeFailed = context.BitwiseOr(
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context.ICompareNotEqual(currValueLow, exValueLow),
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context.ICompareNotEqual(currValueHigh, exValueHigh));
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}
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else
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{
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storeFailed = context.ICompareNotEqual(currValue, exValue);
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}
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SetRs(storeFailed);
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context.MarkLabel(lblExit);
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}
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else
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{
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InstEmitMemoryHelper.EmitWriteIntAligned(context, address, value, size);
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}
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}
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public static void EmitClearExclusive(ArmEmitterContext context)
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{
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Operand arg0 = context.LoadArgument(OperandType.I64, 0);
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Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset()));
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// We store ULONG max to force any exclusive address checks to fail,
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// since this value is not aligned to the ERG mask.
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context.Store(exAddrPtr, Const(ulong.MaxValue));
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}
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private static long GetExclusiveAddressMask() => ~((4L << ErgSizeLog2) - 1);
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}
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}
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