mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-07-15 14:16:16 +02:00
5e0f8e8738
* Implement JIT Arm64 backend * PPTC version bump * Address some feedback from Arm64 JIT PR * Address even more PR feedback * Remove unused IsPageAligned function * Sync Qc flag before calls * Fix comment and remove unused enum * Address riperiperi PR feedback * Delete Breakpoint IR instruction that was only implemented for Arm64
662 lines
26 KiB
C#
662 lines
26 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using System;
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using System.Diagnostics;
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namespace ARMeilleure.CodeGen.Arm64
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{
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static class CodeGeneratorIntrinsic
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{
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public static void GenerateOperation(CodeGenContext context, Operation operation)
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{
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Intrinsic intrin = operation.Intrinsic;
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IntrinsicInfo info = IntrinsicTable.GetInfo(intrin & ~(Intrinsic.Arm64VTypeMask | Intrinsic.Arm64VSizeMask));
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switch (info.Type)
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{
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case IntrinsicType.ScalarUnary:
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GenerateVectorUnary(
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context,
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0,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(0));
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break;
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case IntrinsicType.ScalarUnaryByElem:
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Debug.Assert(operation.GetSource(1).Kind == OperandKind.Constant);
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GenerateVectorUnaryByElem(
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context,
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0,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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(uint)operation.GetSource(1).AsInt32(),
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operation.Destination,
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operation.GetSource(0));
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break;
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case IntrinsicType.ScalarBinary:
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GenerateVectorBinary(
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context,
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0,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(0),
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operation.GetSource(1));
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break;
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case IntrinsicType.ScalarBinaryFPByElem:
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Debug.Assert(operation.GetSource(2).Kind == OperandKind.Constant);
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GenerateVectorBinaryFPByElem(
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context,
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0,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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(uint)operation.GetSource(2).AsInt32(),
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operation.Destination,
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operation.GetSource(0),
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operation.GetSource(1));
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break;
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case IntrinsicType.ScalarBinaryRd:
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GenerateVectorUnary(
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context,
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0,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(1));
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break;
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case IntrinsicType.ScalarBinaryShl:
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Debug.Assert(operation.GetSource(1).Kind == OperandKind.Constant);
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GenerateVectorBinaryShlImm(
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context,
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0,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(0),
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(uint)operation.GetSource(1).AsInt32());
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break;
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case IntrinsicType.ScalarBinaryShr:
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Debug.Assert(operation.GetSource(1).Kind == OperandKind.Constant);
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GenerateVectorBinaryShrImm(
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context,
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0,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(0),
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(uint)operation.GetSource(1).AsInt32());
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break;
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case IntrinsicType.ScalarFPCompare:
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GenerateScalarFPCompare(
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context,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(0),
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operation.GetSource(1));
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break;
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case IntrinsicType.ScalarFPConvFixed:
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Debug.Assert(operation.GetSource(1).Kind == OperandKind.Constant);
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GenerateVectorBinaryShrImm(
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context,
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0,
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((uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift) + 2u,
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info.Inst,
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operation.Destination,
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operation.GetSource(0),
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(uint)operation.GetSource(1).AsInt32());
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break;
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case IntrinsicType.ScalarFPConvFixedGpr:
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Debug.Assert(operation.GetSource(1).Kind == OperandKind.Constant);
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GenerateScalarFPConvGpr(
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context,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(0),
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(uint)operation.GetSource(1).AsInt32());
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break;
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case IntrinsicType.ScalarFPConvGpr:
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GenerateScalarFPConvGpr(
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context,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(0));
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break;
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case IntrinsicType.ScalarTernary:
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GenerateScalarTernary(
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context,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(1),
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operation.GetSource(2),
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operation.GetSource(0));
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break;
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case IntrinsicType.ScalarTernaryFPRdByElem:
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Debug.Assert(operation.GetSource(3).Kind == OperandKind.Constant);
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GenerateVectorBinaryFPByElem(
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context,
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0,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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(uint)operation.GetSource(3).AsInt32(),
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operation.Destination,
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operation.GetSource(1),
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operation.GetSource(2));
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break;
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case IntrinsicType.ScalarTernaryShlRd:
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Debug.Assert(operation.GetSource(2).Kind == OperandKind.Constant);
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GenerateVectorBinaryShlImm(
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context,
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0,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(1),
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(uint)operation.GetSource(2).AsInt32());
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break;
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case IntrinsicType.ScalarTernaryShrRd:
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Debug.Assert(operation.GetSource(2).Kind == OperandKind.Constant);
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GenerateVectorBinaryShrImm(
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context,
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0,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(1),
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(uint)operation.GetSource(2).AsInt32());
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break;
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case IntrinsicType.VectorUnary:
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GenerateVectorUnary(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(0));
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break;
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case IntrinsicType.VectorUnaryByElem:
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Debug.Assert(operation.GetSource(1).Kind == OperandKind.Constant);
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GenerateVectorUnaryByElem(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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(uint)operation.GetSource(1).AsInt32(),
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operation.Destination,
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operation.GetSource(0));
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break;
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case IntrinsicType.VectorBinary:
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GenerateVectorBinary(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(0),
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operation.GetSource(1));
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break;
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case IntrinsicType.VectorBinaryBitwise:
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GenerateVectorBinary(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(0),
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operation.GetSource(1));
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break;
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case IntrinsicType.VectorBinaryByElem:
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Debug.Assert(operation.GetSource(2).Kind == OperandKind.Constant);
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GenerateVectorBinaryByElem(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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(uint)operation.GetSource(2).AsInt32(),
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operation.Destination,
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operation.GetSource(0),
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operation.GetSource(1));
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break;
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case IntrinsicType.VectorBinaryFPByElem:
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Debug.Assert(operation.GetSource(2).Kind == OperandKind.Constant);
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GenerateVectorBinaryFPByElem(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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(uint)operation.GetSource(2).AsInt32(),
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operation.Destination,
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operation.GetSource(0),
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operation.GetSource(1));
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break;
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case IntrinsicType.VectorBinaryRd:
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GenerateVectorUnary(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(1));
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break;
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case IntrinsicType.VectorBinaryShl:
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Debug.Assert(operation.GetSource(1).Kind == OperandKind.Constant);
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GenerateVectorBinaryShlImm(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(0),
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(uint)operation.GetSource(1).AsInt32());
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break;
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case IntrinsicType.VectorBinaryShr:
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Debug.Assert(operation.GetSource(1).Kind == OperandKind.Constant);
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GenerateVectorBinaryShrImm(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(0),
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(uint)operation.GetSource(1).AsInt32());
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break;
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case IntrinsicType.VectorFPConvFixed:
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Debug.Assert(operation.GetSource(1).Kind == OperandKind.Constant);
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GenerateVectorBinaryShrImm(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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((uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift) + 2u,
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info.Inst,
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operation.Destination,
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operation.GetSource(0),
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(uint)operation.GetSource(1).AsInt32());
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break;
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case IntrinsicType.VectorInsertByElem:
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Debug.Assert(operation.GetSource(1).Kind == OperandKind.Constant);
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Debug.Assert(operation.GetSource(3).Kind == OperandKind.Constant);
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GenerateVectorInsertByElem(
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context,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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(uint)operation.GetSource(3).AsInt32(),
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(uint)operation.GetSource(1).AsInt32(),
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operation.Destination,
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operation.GetSource(2));
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break;
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case IntrinsicType.VectorLookupTable:
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Debug.Assert((uint)(operation.SourcesCount - 2) <= 3);
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for (int i = 1; i < operation.SourcesCount - 1; i++)
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{
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Register currReg = operation.GetSource(i).GetRegister();
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Register prevReg = operation.GetSource(i - 1).GetRegister();
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Debug.Assert(prevReg.Index + 1 == currReg.Index && currReg.Type == RegisterType.Vector);
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}
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GenerateVectorBinary(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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info.Inst | ((uint)(operation.SourcesCount - 2) << 13),
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operation.Destination,
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operation.GetSource(0),
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operation.GetSource(operation.SourcesCount - 1));
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break;
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case IntrinsicType.VectorTernaryFPRdByElem:
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Debug.Assert(operation.GetSource(3).Kind == OperandKind.Constant);
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GenerateVectorBinaryFPByElem(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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(uint)operation.GetSource(3).AsInt32(),
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operation.Destination,
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operation.GetSource(1),
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operation.GetSource(2));
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break;
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case IntrinsicType.VectorTernaryRd:
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GenerateVectorBinary(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(1),
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operation.GetSource(2));
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break;
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case IntrinsicType.VectorTernaryRdBitwise:
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GenerateVectorBinary(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(1),
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operation.GetSource(2));
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break;
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case IntrinsicType.VectorTernaryRdByElem:
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Debug.Assert(operation.GetSource(3).Kind == OperandKind.Constant);
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GenerateVectorBinaryByElem(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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(uint)operation.GetSource(3).AsInt32(),
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operation.Destination,
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operation.GetSource(1),
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operation.GetSource(2));
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break;
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case IntrinsicType.VectorTernaryShlRd:
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Debug.Assert(operation.GetSource(2).Kind == OperandKind.Constant);
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GenerateVectorBinaryShlImm(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(1),
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(uint)operation.GetSource(2).AsInt32());
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break;
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case IntrinsicType.VectorTernaryShrRd:
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Debug.Assert(operation.GetSource(2).Kind == OperandKind.Constant);
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GenerateVectorBinaryShrImm(
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context,
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(uint)(intrin & Intrinsic.Arm64VTypeMask) >> (int)Intrinsic.Arm64VTypeShift,
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(uint)(intrin & Intrinsic.Arm64VSizeMask) >> (int)Intrinsic.Arm64VSizeShift,
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info.Inst,
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operation.Destination,
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operation.GetSource(1),
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(uint)operation.GetSource(2).AsInt32());
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break;
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case IntrinsicType.GetRegister:
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context.Assembler.WriteInstruction(info.Inst, operation.Destination);
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break;
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case IntrinsicType.SetRegister:
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context.Assembler.WriteInstruction(info.Inst, operation.GetSource(0));
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break;
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default:
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throw new NotImplementedException(info.Type.ToString());
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}
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}
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private static void GenerateScalarFPCompare(
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CodeGenContext context,
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uint sz,
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uint instruction,
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Operand dest,
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Operand rn,
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Operand rm)
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{
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instruction |= (sz << 22);
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if (rm.Kind == OperandKind.Constant && rm.Value == 0)
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{
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instruction |= 0b1000;
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rm = rn;
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}
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context.Assembler.WriteInstructionRm16NoRet(instruction, rn, rm);
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context.Assembler.Mrs(dest, 1, 3, 4, 2, 0);
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}
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private static void GenerateScalarFPConvGpr(
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CodeGenContext context,
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uint sz,
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uint instruction,
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Operand rd,
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Operand rn)
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{
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instruction |= (sz << 22);
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if (rd.Type.IsInteger())
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{
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context.Assembler.WriteInstructionAuto(instruction, rd, rn);
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}
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else
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{
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if (rn.Type == OperandType.I64)
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{
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instruction |= Assembler.SfFlag;
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}
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context.Assembler.WriteInstruction(instruction, rd, rn);
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}
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}
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private static void GenerateScalarFPConvGpr(
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CodeGenContext context,
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uint sz,
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uint instruction,
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Operand rd,
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Operand rn,
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uint fBits)
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{
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Debug.Assert(fBits <= 64);
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instruction |= (sz << 22);
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instruction |= (64 - fBits) << 10;
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if (rd.Type.IsInteger())
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{
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Debug.Assert(rd.Type != OperandType.I32 || fBits <= 32);
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context.Assembler.WriteInstructionAuto(instruction, rd, rn);
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}
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else
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{
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if (rn.Type == OperandType.I64)
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{
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instruction |= Assembler.SfFlag;
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}
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else
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{
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Debug.Assert(fBits <= 32);
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}
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context.Assembler.WriteInstruction(instruction, rd, rn);
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}
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}
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private static void GenerateScalarTernary(
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CodeGenContext context,
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uint sz,
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uint instruction,
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Operand rd,
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Operand rn,
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Operand rm,
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Operand ra)
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{
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instruction |= (sz << 22);
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context.Assembler.WriteInstruction(instruction, rd, rn, rm, ra);
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}
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private static void GenerateVectorUnary(
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CodeGenContext context,
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uint q,
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uint sz,
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uint instruction,
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Operand rd,
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Operand rn)
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{
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instruction |= (q << 30) | (sz << 22);
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context.Assembler.WriteInstruction(instruction, rd, rn);
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}
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private static void GenerateVectorUnaryByElem(
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CodeGenContext context,
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uint q,
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uint sz,
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uint instruction,
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uint srcIndex,
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Operand rd,
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Operand rn)
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{
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uint imm5 = (srcIndex << ((int)sz + 1)) | (1u << (int)sz);
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instruction |= (q << 30) | (imm5 << 16);
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context.Assembler.WriteInstruction(instruction, rd, rn);
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}
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private static void GenerateVectorBinary(
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CodeGenContext context,
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uint q,
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uint instruction,
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Operand rd,
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Operand rn,
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Operand rm)
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{
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instruction |= (q << 30);
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context.Assembler.WriteInstructionRm16(instruction, rd, rn, rm);
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}
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private static void GenerateVectorBinary(
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CodeGenContext context,
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uint q,
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uint sz,
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uint instruction,
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Operand rd,
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Operand rn,
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|
Operand rm)
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{
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instruction |= (q << 30) | (sz << 22);
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context.Assembler.WriteInstructionRm16(instruction, rd, rn, rm);
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}
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private static void GenerateVectorBinaryByElem(
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CodeGenContext context,
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uint q,
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uint size,
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uint instruction,
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uint srcIndex,
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Operand rd,
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Operand rn,
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Operand rm)
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{
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instruction |= (q << 30) | (size << 22);
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if (size == 2)
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{
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instruction |= ((srcIndex & 1) << 21) | ((srcIndex & 2) << 10);
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}
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else
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{
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instruction |= ((srcIndex & 3) << 20) | ((srcIndex & 4) << 9);
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}
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context.Assembler.WriteInstructionRm16(instruction, rd, rn, rm);
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}
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private static void GenerateVectorBinaryFPByElem(
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CodeGenContext context,
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uint q,
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uint sz,
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uint instruction,
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uint srcIndex,
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Operand rd,
|
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Operand rn,
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Operand rm)
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{
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instruction |= (q << 30) | (sz << 22);
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if (sz != 0)
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{
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instruction |= (srcIndex & 1) << 11;
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}
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else
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{
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instruction |= ((srcIndex & 1) << 21) | ((srcIndex & 2) << 10);
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}
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context.Assembler.WriteInstructionRm16(instruction, rd, rn, rm);
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}
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private static void GenerateVectorBinaryShlImm(
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CodeGenContext context,
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uint q,
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uint sz,
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uint instruction,
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Operand rd,
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Operand rn,
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uint shift)
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{
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instruction |= (q << 30);
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Debug.Assert(shift >= 0 && shift < (8u << (int)sz));
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uint imm = (8u << (int)sz) | (shift & (0x3fu >> (int)(3 - sz)));
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instruction |= (imm << 16);
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context.Assembler.WriteInstruction(instruction, rd, rn);
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}
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private static void GenerateVectorBinaryShrImm(
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CodeGenContext context,
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uint q,
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|
uint sz,
|
|
uint instruction,
|
|
Operand rd,
|
|
Operand rn,
|
|
uint shift)
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|
{
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instruction |= (q << 30);
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Debug.Assert(shift > 0 && shift <= (8u << (int)sz));
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uint imm = (8u << (int)sz) | ((8u << (int)sz) - shift);
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instruction |= (imm << 16);
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context.Assembler.WriteInstruction(instruction, rd, rn);
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}
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private static void GenerateVectorInsertByElem(
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CodeGenContext context,
|
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uint sz,
|
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uint instruction,
|
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uint srcIndex,
|
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uint dstIndex,
|
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Operand rd,
|
|
Operand rn)
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{
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uint imm4 = srcIndex << (int)sz;
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uint imm5 = (dstIndex << ((int)sz + 1)) | (1u << (int)sz);
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instruction |= imm4 << 11;
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instruction |= imm5 << 16;
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context.Assembler.WriteInstruction(instruction, rd, rn);
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}
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}
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} |