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* Get rid of Reflection.Emit dependency on CPU and Shader projects * Remove useless private sets * Missed those due to the alignment
74 lines
2 KiB
C#
74 lines
2 KiB
C#
namespace ARMeilleure.Decoders
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{
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class OpCode32SimdMemMult : OpCode32
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{
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public int Rn { get; }
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public int Vd { get; }
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public int RegisterRange { get; }
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public int Offset { get; }
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public int PostOffset { get; }
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public bool IsLoad { get; }
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public bool DoubleWidth { get; }
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public bool Add { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode);
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public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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Rn = (opCode >> 16) & 0xf;
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bool isLoad = (opCode & (1 << 20)) != 0;
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bool w = (opCode & (1 << 21)) != 0;
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bool u = (opCode & (1 << 23)) != 0;
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bool p = (opCode & (1 << 24)) != 0;
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if (p == u && w)
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{
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Instruction = InstDescriptor.Undefined;
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return;
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}
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DoubleWidth = (opCode & (1 << 8)) != 0;
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if (!DoubleWidth)
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{
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Vd = ((opCode >> 22) & 0x1) | ((opCode >> 11) & 0x1e);
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}
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else
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{
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Vd = ((opCode >> 18) & 0x10) | ((opCode >> 12) & 0xf);
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}
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Add = u;
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RegisterRange = opCode & 0xff;
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int regsSize = RegisterRange * 4; // Double mode is still measured in single register size.
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if (!u)
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{
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Offset -= regsSize;
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}
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if (w)
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{
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PostOffset = u ? regsSize : -regsSize;
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}
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else
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{
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PostOffset = 0;
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}
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IsLoad = isLoad;
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int regs = DoubleWidth ? RegisterRange / 2 : RegisterRange;
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if (RegisterRange == 0 || RegisterRange > 32 || Vd + regs > 32)
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{
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Instruction = InstDescriptor.Undefined;
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}
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}
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}
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}
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