mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-09-17 13:18:51 +02:00
* Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions * Address PR feedback * Address PR feedback * Remove another useless temp var * nit: Alignment * Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount() * Fix encodings and move flag bit test out of the loop
417 lines
No EOL
12 KiB
C#
417 lines
No EOL
12 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using static ChocolArm64.Instruction.AInstEmitSimdHelper;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void Shl_S(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorExtractZx(Context, Op.Rn, 0, Op.Size);
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Context.EmitLdc_I4(GetImmShl(Op));
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Context.Emit(OpCodes.Shl);
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EmitScalarSet(Context, Op.Rd, Op.Size);
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}
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public static void Shl_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShImmBinaryZx(Context, () => Context.Emit(OpCodes.Shl), GetImmShl(Op));
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}
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public static void Shll_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Shift = 8 << Op.Size;
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EmitVectorShImmWidenBinaryZx(Context, () => Context.Emit(OpCodes.Shl), Shift);
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}
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public static void Shrn_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShImmNarrowBinaryZx(Context, () => Context.Emit(OpCodes.Shr_Un), GetImmShr(Op));
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}
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public static void Sli_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int Shift = GetImmShl(Op);
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ulong Mask = Shift != 0 ? ulong.MaxValue >> (64 - Shift) : 0;
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
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Context.EmitLdc_I4(Shift);
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Context.Emit(OpCodes.Shl);
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EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
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Context.EmitLdc_I8((long)Mask);
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Context.Emit(OpCodes.And);
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Context.Emit(OpCodes.Or);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Sqrshrn_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = GetImmShr(Op);
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long RoundConst = 1L << (Shift - 1);
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Action Emit = () =>
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{
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Context.EmitLdc_I8(RoundConst);
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Context.Emit(OpCodes.Add);
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Context.EmitLdc_I4(Shift);
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Context.Emit(OpCodes.Shr);
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};
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EmitVectorSaturatingNarrowOpSxSx(Context, Emit);
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}
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public static void Srshr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = GetImmShr(Op);
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long RoundConst = 1L << (Shift - 1);
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EmitVectorRoundShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), Shift, RoundConst);
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}
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public static void Sshl_V(AILEmitterCtx Context)
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{
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EmitVectorShl(Context, Signed: true);
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}
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public static void Sshll_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShImmWidenBinarySx(Context, () => Context.Emit(OpCodes.Shl), GetImmShl(Op));
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}
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public static void Sshr_S(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorExtractSx(Context, Op.Rn, 0, Op.Size);
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.Emit(OpCodes.Shr);
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EmitScalarSet(Context, Op.Rd, Op.Size);
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}
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public static void Sshr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), GetImmShr(Op));
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}
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public static void Ssra_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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Action Emit = () =>
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{
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Context.Emit(OpCodes.Shr);
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Context.Emit(OpCodes.Add);
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};
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EmitVectorShImmTernarySx(Context, Emit, GetImmShr(Op));
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}
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public static void Ushl_V(AILEmitterCtx Context)
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{
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EmitVectorShl(Context, Signed: false);
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}
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public static void Ushll_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShImmWidenBinaryZx(Context, () => Context.Emit(OpCodes.Shl), GetImmShl(Op));
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}
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public static void Ushr_S(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitScalarUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.Emit(OpCodes.Shr_Un);
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});
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}
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public static void Ushr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.Emit(OpCodes.Shr_Un);
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});
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}
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public static void Usra_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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Action Emit = () =>
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{
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Context.EmitLdc_I4(GetImmShr(Op));
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Context.Emit(OpCodes.Shr_Un);
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Context.Emit(OpCodes.Add);
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};
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EmitVectorOp(Context, Emit, OperFlags.RdRn, Signed: false);
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}
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private static void EmitVectorShl(AILEmitterCtx Context, bool Signed)
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{
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//This instruction shifts the value on vector A by the number of bits
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//specified on the signed, lower 8 bits of vector B. If the shift value
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//is greater or equal to the data size of each lane, then the result is zero.
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//Additionally, negative shifts produces right shifts by the negated shift value.
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int MaxShift = 8 << Op.Size;
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Action Emit = () =>
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{
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AILLabel LblShl = new AILLabel();
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AILLabel LblZero = new AILLabel();
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AILLabel LblEnd = new AILLabel();
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void EmitShift(OpCode ILOp)
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{
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I4(MaxShift);
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Context.Emit(OpCodes.Bge_S, LblZero);
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Context.Emit(ILOp);
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Context.Emit(OpCodes.Br_S, LblEnd);
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}
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Context.Emit(OpCodes.Conv_I1);
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I4(0);
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Context.Emit(OpCodes.Bge_S, LblShl);
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Context.Emit(OpCodes.Neg);
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EmitShift(Signed
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? OpCodes.Shr
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: OpCodes.Shr_Un);
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Context.MarkLabel(LblShl);
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EmitShift(OpCodes.Shl);
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Context.MarkLabel(LblZero);
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Context.Emit(OpCodes.Pop);
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Context.Emit(OpCodes.Pop);
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Context.EmitLdc_I8(0);
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Context.MarkLabel(LblEnd);
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};
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if (Signed)
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{
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EmitVectorBinaryOpSx(Context, Emit);
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}
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else
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{
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EmitVectorBinaryOpZx(Context, Emit);
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}
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}
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[Flags]
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private enum ShImmFlags
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{
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None = 0,
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Signed = 1 << 0,
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Ternary = 1 << 1,
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Rounded = 1 << 2,
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SignedTernary = Signed | Ternary,
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SignedRounded = Signed | Rounded
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}
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private static void EmitVectorShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.Signed);
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}
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private static void EmitVectorShImmTernarySx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.SignedTernary);
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}
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private static void EmitVectorShImmBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.None);
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}
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private static void EmitVectorRoundShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm, long Rc)
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{
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EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.SignedRounded, Rc);
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}
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private static void EmitVectorShImmOp(AILEmitterCtx Context, Action Emit, int Imm, ShImmFlags Flags, long Rc = 0)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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bool Signed = (Flags & ShImmFlags.Signed) != 0;
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bool Ternary = (Flags & ShImmFlags.Ternary) != 0;
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bool Rounded = (Flags & ShImmFlags.Rounded) != 0;
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for (int Index = 0; Index < Elems; Index++)
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{
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if (Ternary)
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{
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EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
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}
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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if (Rounded)
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{
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Context.EmitLdc_I8(Rc);
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Context.Emit(OpCodes.Add);
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}
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Context.EmitLdc_I4(Imm);
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Emit();
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitVectorShImmNarrowBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorShImmNarrowBinaryOp(Context, Emit, Imm, true);
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}
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private static void EmitVectorShImmNarrowBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorShImmNarrowBinaryOp(Context, Emit, Imm, false);
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}
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private static void EmitVectorShImmNarrowBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Signed)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Elems = 8 >> Op.Size;
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, Signed);
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Context.EmitLdc_I4(Imm);
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Emit();
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EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size);
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}
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if (Part == 0)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitVectorShImmWidenBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorShImmWidenBinaryOp(Context, Emit, Imm, true);
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}
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private static void EmitVectorShImmWidenBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
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{
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EmitVectorShImmWidenBinaryOp(Context, Emit, Imm, false);
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}
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private static void EmitVectorShImmWidenBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Signed)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Elems = 8 >> Op.Size;
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtract(Context, Op.Rn, Part + Index, Op.Size, Signed);
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Context.EmitLdc_I4(Imm);
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Emit();
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EmitVectorInsertTmp(Context, Index, Op.Size + 1);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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}
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}
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} |