mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-18 22:58:43 +02:00
* Initial Apple Hypervisor based CPU emulation implementation * Add UseHypervisor Setting * Add basic MacOS support to Avalonia * Fix initialization * Fix GTK build * Fix/silence warnings * Change exceptions to asserts on HvAddressSpaceRange * Replace DllImport with LibraryImport * Fix LibraryImport * Remove unneeded usings * Revert outdated change * Set DiskCacheLoadState when using hypervisor too * Fix HvExecutionContext PC value * Address PR feedback * Use existing entitlements.xml file on distribution folder --------- Co-authored-by: riperiperi <rhy3756547@hotmail.com>
196 lines
6.1 KiB
C#
196 lines
6.1 KiB
C#
using ARMeilleure.State;
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using Ryujinx.Memory;
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using System;
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using System.Runtime.InteropServices;
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using System.Threading;
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namespace Ryujinx.Cpu.AppleHv
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{
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class HvExecutionContextVcpu : IHvExecutionContext
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{
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private static MemoryBlock _setSimdFpRegFuncMem;
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private delegate hv_result_t SetSimdFpReg(ulong vcpu, hv_simd_fp_reg_t reg, in V128 value, IntPtr funcPtr);
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private static SetSimdFpReg _setSimdFpReg;
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private static IntPtr _setSimdFpRegNativePtr;
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static HvExecutionContextVcpu()
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{
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// .NET does not support passing vectors by value, so we need to pass a pointer and use a native
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// function to load the value into a vector register.
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_setSimdFpRegFuncMem = new MemoryBlock(MemoryBlock.GetPageSize());
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_setSimdFpRegFuncMem.Write(0, 0x3DC00040u); // LDR Q0, [X2]
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_setSimdFpRegFuncMem.Write(4, 0xD61F0060u); // BR X3
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_setSimdFpRegFuncMem.Reprotect(0, _setSimdFpRegFuncMem.Size, MemoryPermission.ReadAndExecute);
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_setSimdFpReg = Marshal.GetDelegateForFunctionPointer<SetSimdFpReg>(_setSimdFpRegFuncMem.Pointer);
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if (NativeLibrary.TryLoad(HvApi.LibraryName, out IntPtr hvLibHandle))
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{
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_setSimdFpRegNativePtr = NativeLibrary.GetExport(hvLibHandle, nameof(HvApi.hv_vcpu_set_simd_fp_reg));
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}
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}
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public ulong Pc
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{
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get
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{
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HvApi.hv_vcpu_get_reg(_vcpu, hv_reg_t.HV_REG_PC, out ulong pc).ThrowOnError();
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return pc;
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}
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set
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{
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HvApi.hv_vcpu_set_reg(_vcpu, hv_reg_t.HV_REG_PC, value).ThrowOnError();
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}
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}
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public ulong ElrEl1
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{
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get
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{
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HvApi.hv_vcpu_get_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_ELR_EL1, out ulong elr).ThrowOnError();
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return elr;
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}
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set
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{
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HvApi.hv_vcpu_set_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_ELR_EL1, value).ThrowOnError();
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}
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}
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public ulong EsrEl1
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{
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get
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{
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HvApi.hv_vcpu_get_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_ESR_EL1, out ulong esr).ThrowOnError();
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return esr;
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}
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set
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{
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HvApi.hv_vcpu_set_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_ESR_EL1, value).ThrowOnError();
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}
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}
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public long TpidrEl0
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{
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get
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{
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HvApi.hv_vcpu_get_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_TPIDR_EL0, out ulong tpidrEl0).ThrowOnError();
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return (long)tpidrEl0;
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}
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set
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{
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HvApi.hv_vcpu_set_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_TPIDR_EL0, (ulong)value).ThrowOnError();
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}
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}
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public long TpidrroEl0
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{
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get
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{
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HvApi.hv_vcpu_get_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_TPIDRRO_EL0, out ulong tpidrroEl0).ThrowOnError();
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return (long)tpidrroEl0;
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}
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set
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{
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HvApi.hv_vcpu_set_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_TPIDRRO_EL0, (ulong)value).ThrowOnError();
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}
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}
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public uint Pstate
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{
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get
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{
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HvApi.hv_vcpu_get_reg(_vcpu, hv_reg_t.HV_REG_CPSR, out ulong cpsr).ThrowOnError();
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return (uint)cpsr;
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}
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set
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{
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HvApi.hv_vcpu_set_reg(_vcpu, hv_reg_t.HV_REG_CPSR, (ulong)value).ThrowOnError();
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}
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}
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public uint Fpcr
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{
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get
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{
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HvApi.hv_vcpu_get_reg(_vcpu, hv_reg_t.HV_REG_FPCR, out ulong fpcr).ThrowOnError();
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return (uint)fpcr;
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}
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set
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{
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HvApi.hv_vcpu_set_reg(_vcpu, hv_reg_t.HV_REG_FPCR, (ulong)value).ThrowOnError();
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}
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}
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public uint Fpsr
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{
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get
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{
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HvApi.hv_vcpu_get_reg(_vcpu, hv_reg_t.HV_REG_FPSR, out ulong fpsr).ThrowOnError();
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return (uint)fpsr;
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}
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set
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{
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HvApi.hv_vcpu_set_reg(_vcpu, hv_reg_t.HV_REG_FPSR, (ulong)value).ThrowOnError();
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}
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}
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private ulong _vcpu;
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private int _interruptRequested;
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public HvExecutionContextVcpu(ulong vcpu)
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{
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_vcpu = vcpu;
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}
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public ulong GetX(int index)
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{
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if (index == 31)
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{
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HvApi.hv_vcpu_get_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_SP_EL0, out ulong value).ThrowOnError();
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return value;
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}
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else
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{
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HvApi.hv_vcpu_get_reg(_vcpu, hv_reg_t.HV_REG_X0 + (uint)index, out ulong value).ThrowOnError();
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return value;
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}
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}
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public void SetX(int index, ulong value)
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{
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if (index == 31)
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{
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HvApi.hv_vcpu_set_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_SP_EL0, value).ThrowOnError();
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}
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else
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{
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HvApi.hv_vcpu_set_reg(_vcpu, hv_reg_t.HV_REG_X0 + (uint)index, value).ThrowOnError();
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}
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}
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public V128 GetV(int index)
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{
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HvApi.hv_vcpu_get_simd_fp_reg(_vcpu, hv_simd_fp_reg_t.HV_SIMD_FP_REG_Q0 + (uint)index, out hv_simd_fp_uchar16_t value).ThrowOnError();
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return new V128(value.Low, value.High);
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}
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public void SetV(int index, V128 value)
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{
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_setSimdFpReg(_vcpu, hv_simd_fp_reg_t.HV_SIMD_FP_REG_Q0 + (uint)index, value, _setSimdFpRegNativePtr).ThrowOnError();
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}
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public void RequestInterrupt()
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{
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if (Interlocked.Exchange(ref _interruptRequested, 1) == 0)
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{
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ulong vcpu = _vcpu;
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HvApi.hv_vcpus_exit(ref vcpu, 1);
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}
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}
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public bool GetAndClearInterruptRequested()
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{
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return Interlocked.Exchange(ref _interruptRequested, 0) != 0;
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}
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}
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} |