a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
190 lines
7.7 KiB
C#
190 lines
7.7 KiB
C#
#define SimdRegElem
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using ARMeilleure.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdRegElem")]
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public sealed class CpuTestSimdRegElem : CpuTest
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{
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#if SimdRegElem
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#region "ValueSource (Types)"
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private static ulong[] _2S_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
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0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _4H_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
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0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _Mla_Mls_Mul_Ve_4H_8H_()
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{
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return new uint[]
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{
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0x2F400000u, // MLA V0.4H, V0.4H, V0.H[0]
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0x2F404000u, // MLS V0.4H, V0.4H, V0.H[0]
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0x0F408000u // MUL V0.4H, V0.4H, V0.H[0]
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};
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}
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private static uint[] _Mla_Mls_Mul_Ve_2S_4S_()
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{
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return new uint[]
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{
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0x2F800000u, // MLA V0.2S, V0.2S, V0.S[0]
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0x2F804000u, // MLS V0.2S, V0.2S, V0.S[0]
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0x0F808000u // MUL V0.2S, V0.2S, V0.S[0]
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};
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}
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private static uint[] _SU_Mlal_Mlsl_Mull_Ve_4H4S_8H4S_()
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{
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return new uint[]
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{
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0x0F402000u, // SMLAL V0.4S, V0.4H, V0.H[0]
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0x0F406000u, // SMLSL V0.4S, V0.4H, V0.H[0]
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0x0F40A000u, // SMULL V0.4S, V0.4H, V0.H[0]
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0x2F402000u, // UMLAL V0.4S, V0.4H, V0.H[0]
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0x2F406000u, // UMLSL V0.4S, V0.4H, V0.H[0]
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0x2F40A000u // UMULL V0.4S, V0.4H, V0.H[0]
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};
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}
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private static uint[] _SU_Mlal_Mlsl_Mull_Ve_2S2D_4S2D_()
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{
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return new uint[]
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{
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0x0F802000u, // SMLAL V0.2D, V0.2S, V0.S[0]
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0x0F806000u, // SMLSL V0.2D, V0.2S, V0.S[0]
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0x0F80A000u, // SMULL V0.2D, V0.2S, V0.S[0]
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0x2F802000u, // UMLAL V0.2D, V0.2S, V0.S[0]
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0x2F806000u, // UMLSL V0.2D, V0.2S, V0.S[0]
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0x2F80A000u // UMULL V0.2D, V0.2S, V0.S[0]
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};
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}
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#endregion
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private const int RndCnt = 2;
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private const int RndCntIndex = 2;
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[Test, Pairwise]
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public void Mla_Mls_Mul_Ve_4H_8H([ValueSource("_Mla_Mls_Mul_Ve_4H_8H_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
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[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <4H, 8H>
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{
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uint h = (index >> 2) & 1;
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uint l = (index >> 1) & 1;
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uint m = index & 1;
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opcodes |= ((rm & 15) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (l << 21) | (m << 20) | (h << 11);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a * q);
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V128 v2 = MakeVectorE0E1(b, b * h);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Mla_Mls_Mul_Ve_2S_4S([ValueSource("_Mla_Mls_Mul_Ve_2S_4S_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong b,
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[Values(0u, 1u, 2u, 3u)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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uint h = (index >> 1) & 1;
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uint l = index & 1;
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opcodes |= ((rm & 15) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (l << 21) | (h << 11);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, a * q);
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V128 v2 = MakeVectorE0E1(b, b * h);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void SU_Mlal_Mlsl_Mull_Ve_4H4S_8H4S([ValueSource("_SU_Mlal_Mlsl_Mull_Ve_4H4S_8H4S_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong a,
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[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
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[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <4H4S, 8H4S>
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{
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uint h = (index >> 2) & 1;
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uint l = (index >> 1) & 1;
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uint m = index & 1;
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opcodes |= ((rm & 15) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (l << 21) | (m << 20) | (h << 11);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
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V128 v2 = MakeVectorE0E1(b, b * h);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void SU_Mlal_Mlsl_Mull_Ve_2S2D_4S2D([ValueSource("_SU_Mlal_Mlsl_Mull_Ve_2S2D_4S2D_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong b,
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[Values(0u, 1u, 2u, 3u)] uint index,
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[Values(0b0u, 0b1u)] uint q) // <2S2D, 4S2D>
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{
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uint h = (index >> 1) & 1;
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uint l = index & 1;
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opcodes |= ((rm & 15) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (l << 21) | (h << 11);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(q == 0u ? a : 0ul, q == 1u ? a : 0ul);
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V128 v2 = MakeVectorE0E1(b, b * h);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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