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* Add initial implementation of the Tamper Machine * Implement Atmosphere opcodes 0, 4 and 9 * Add missing TamperCompilationException class * Implement Atmosphere conditional and loop opcodes 1, 2 and 3 * Inplement input conditional opcode 8 * Add register store opcode A * Implement extended pause/resume opcodes FF0 and FF1 * Implement extended log opcode FFF * Implement extended register conditional opcode C0 * Refactor TamperProgram to an interface * Moved Atmosphere classes to a separate subdirectory * Fix OpProcCtrl class not setting process * Implement extended register save/restore opcodes C1, C2 and C3 * Refactor code emitters to separate classes * Supress memory access errors from the Tamper Machine * Add debug information to tamper register and memory writes * Add block stack check to Atmosphere Cheat compiler * Add handheld input support to Tamper Machine * Fix code styling * Fix build id and cheat case mismatch * Fix invalid immediate size selection * Print build ids of the title * Prevent Tamper Machine from change code regions * Remove Atmosphere namespace * Remove empty cheats from the list * Prevent code modification without disabling the tampering * Fix missing addressing mode in LoadRegisterWithMemory * Fix wrong addressing in RegisterConditional * Add name to the tamper machine thread * Fix code styling
106 lines
5.1 KiB
C#
106 lines
5.1 KiB
C#
using Ryujinx.HLE.Exceptions;
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using Ryujinx.HLE.HOS.Tamper.Conditions;
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using Ryujinx.HLE.HOS.Tamper.Operations;
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namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
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{
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/// <summary>
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/// Code type 0xC0 performs a comparison of the contents of a register and another value.
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/// This code support multiple operand types, see below. If the condition is not met,
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/// all instructions until the appropriate conditional block terminator are skipped.
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/// </summary>
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class RegisterConditional
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{
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private const int OperationWidthIndex = 2;
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private const int ComparisonTypeIndex = 3;
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private const int SourceRegisterIndex = 4;
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private const int OperandTypeIndex = 5;
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private const int RegisterOrMemoryRegionIndex = 6;
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private const int OffsetImmediateIndex = 7;
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private const int ValueImmediateIndex = 8;
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private const int MemoryRegionWithOffsetImmediate = 0;
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private const int MemoryRegionWithOffsetRegister = 1;
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private const int AddressRegisterWithOffsetImmediate = 2;
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private const int AddressRegisterWithOffsetRegister = 3;
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private const int OffsetImmediate = 4;
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private const int AddressRegister = 5;
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private const int OffsetImmediateSize = 9;
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private const int ValueImmediateSize8 = 8;
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private const int ValueImmediateSize16 = 16;
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public static ICondition Emit(byte[] instruction, CompilationContext context)
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{
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// C0TcSX##
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// C0TcS0Ma aaaaaaaa
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// C0TcS1Mr
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// C0TcS2Ra aaaaaaaa
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// C0TcS3Rr
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// C0TcS400 VVVVVVVV (VVVVVVVV)
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// C0TcS5X0
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// T: Width of memory write(1, 2, 4, or 8 bytes).
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// c: Condition to use, see below.
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// S: Source Register.
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// X: Operand Type, see below.
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// M: Memory Type(operand types 0 and 1).
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// R: Address Register(operand types 2 and 3).
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// a: Relative Address(operand types 0 and 2).
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// r: Offset Register(operand types 1 and 3).
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// X: Other Register(operand type 5).
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// V: Value to compare to(operand type 4).
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byte operationWidth = instruction[OperationWidthIndex];
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Comparison comparison = (Comparison)instruction[ComparisonTypeIndex];
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Register sourceRegister = context.GetRegister(instruction[SourceRegisterIndex]);
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byte operandType = instruction[OperandTypeIndex];
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byte registerOrMemoryRegion = instruction[RegisterOrMemoryRegionIndex];
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byte offsetRegisterIndex = instruction[OffsetImmediateIndex];
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ulong offsetImmediate;
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ulong valueImmediate;
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int valueImmediateSize;
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Register addressRegister;
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Register offsetRegister;
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IOperand sourceOperand;
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switch (operandType)
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{
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case MemoryRegionWithOffsetImmediate:
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// *(?x + #a)
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offsetImmediate = InstructionHelper.GetImmediate(instruction, OffsetImmediateIndex, OffsetImmediateSize);
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sourceOperand = MemoryHelper.EmitPointer((MemoryRegion)registerOrMemoryRegion, offsetImmediate, context);
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break;
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case MemoryRegionWithOffsetRegister:
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// *(?x + $r)
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offsetRegister = context.GetRegister(offsetRegisterIndex);
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sourceOperand = MemoryHelper.EmitPointer((MemoryRegion)registerOrMemoryRegion, offsetRegister, context);
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break;
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case AddressRegisterWithOffsetImmediate:
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// *($R + #a)
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addressRegister = context.GetRegister(registerOrMemoryRegion);
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offsetImmediate = InstructionHelper.GetImmediate(instruction, OffsetImmediateIndex, OffsetImmediateSize);
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sourceOperand = MemoryHelper.EmitPointer(addressRegister, offsetImmediate, context);
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break;
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case AddressRegisterWithOffsetRegister:
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// *($R + $r)
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addressRegister = context.GetRegister(registerOrMemoryRegion);
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offsetRegister = context.GetRegister(offsetRegisterIndex);
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sourceOperand = MemoryHelper.EmitPointer(addressRegister, offsetRegister, context);
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break;
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case OffsetImmediate:
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valueImmediateSize = operationWidth <= 4 ? ValueImmediateSize8 : ValueImmediateSize16;
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valueImmediate = InstructionHelper.GetImmediate(instruction, ValueImmediateIndex, valueImmediateSize);
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sourceOperand = new Value<ulong>(valueImmediate);
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break;
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case AddressRegister:
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// $V
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sourceOperand = context.GetRegister(registerOrMemoryRegion);
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break;
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default:
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throw new TamperCompilationException($"Invalid operand type {operandType} in Atmosphere cheat");
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}
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return InstructionHelper.CreateCondition(comparison, operationWidth, sourceRegister, sourceOperand);
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}
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}
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}
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