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https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-20 07:38:42 +02:00
142 lines
5.2 KiB
C#
142 lines
5.2 KiB
C#
using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Instructions
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{
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static partial class InstEmit
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{
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public static void Mov(EmitterContext context)
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{
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context.Copy(GetDest(context), GetSrcB(context));
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}
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public static void R2p(EmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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bool isCC = op.RawOpCode.Extract(40);
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int shift = op.RawOpCode.Extract(41, 2) * 8;
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Operand value = GetSrcA(context);
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Operand mask = GetSrcB(context);
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Operand Test(Operand value, int bit)
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{
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return context.ICompareNotEqual(context.BitwiseAnd(value, Const(1 << bit)), Const(0));
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}
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if (isCC)
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{
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// TODO: Support Register to condition code flags copy.
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context.Config.PrintLog("R2P.CC not implemented.");
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}
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else
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{
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for (int bit = 0; bit < 7; bit++)
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{
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Operand pred = Register(bit, RegisterType.Predicate);
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Operand res = context.ConditionalSelect(Test(mask, bit), Test(value, bit + shift), pred);
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context.Copy(pred, res);
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}
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}
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}
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public static void S2r(EmitterContext context)
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{
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// TODO: Better impl.
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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SystemRegister sysReg = (SystemRegister)op.RawOpCode.Extract(20, 8);
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Operand src;
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switch (sysReg)
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{
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case SystemRegister.LaneId: src = Attribute(AttributeConsts.LaneId); break;
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// TODO: Use value from Y direction GPU register.
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case SystemRegister.YDirection: src = ConstF(1); break;
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case SystemRegister.ThreadId:
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{
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Operand tidX = Attribute(AttributeConsts.ThreadIdX);
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Operand tidY = Attribute(AttributeConsts.ThreadIdY);
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Operand tidZ = Attribute(AttributeConsts.ThreadIdZ);
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tidY = context.ShiftLeft(tidY, Const(16));
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tidZ = context.ShiftLeft(tidZ, Const(26));
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src = context.BitwiseOr(tidX, context.BitwiseOr(tidY, tidZ));
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break;
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}
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case SystemRegister.ThreadIdX: src = Attribute(AttributeConsts.ThreadIdX); break;
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case SystemRegister.ThreadIdY: src = Attribute(AttributeConsts.ThreadIdY); break;
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case SystemRegister.ThreadIdZ: src = Attribute(AttributeConsts.ThreadIdZ); break;
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case SystemRegister.CtaIdX: src = Attribute(AttributeConsts.CtaIdX); break;
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case SystemRegister.CtaIdY: src = Attribute(AttributeConsts.CtaIdY); break;
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case SystemRegister.CtaIdZ: src = Attribute(AttributeConsts.CtaIdZ); break;
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case SystemRegister.EqMask: src = Attribute(AttributeConsts.EqMask); break;
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case SystemRegister.LtMask: src = Attribute(AttributeConsts.LtMask); break;
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case SystemRegister.LeMask: src = Attribute(AttributeConsts.LeMask); break;
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case SystemRegister.GtMask: src = Attribute(AttributeConsts.GtMask); break;
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case SystemRegister.GeMask: src = Attribute(AttributeConsts.GeMask); break;
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default: src = Const(0); break;
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}
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context.Copy(GetDest(context), src);
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}
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public static void Sel(EmitterContext context)
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{
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Operand pred = GetPredicate39(context);
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Operand srcA = GetSrcA(context);
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Operand srcB = GetSrcB(context);
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Operand res = context.ConditionalSelect(pred, srcA, srcB);
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context.Copy(GetDest(context), res);
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}
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public static void Shfl(EmitterContext context)
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{
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OpCodeShuffle op = (OpCodeShuffle)context.CurrOp;
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Operand pred = Register(op.Predicate48);
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Operand srcA = GetSrcA(context);
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Operand srcB = op.IsBImmediate ? Const(op.ImmediateB) : Register(op.Rb);
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Operand srcC = op.IsCImmediate ? Const(op.ImmediateC) : Register(op.Rc);
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Operand res = null;
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switch (op.ShuffleType)
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{
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case ShuffleType.Indexed:
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res = context.Shuffle(srcA, srcB, srcC);
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break;
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case ShuffleType.Up:
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res = context.ShuffleUp(srcA, srcB, srcC);
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break;
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case ShuffleType.Down:
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res = context.ShuffleDown(srcA, srcB, srcC);
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break;
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case ShuffleType.Butterfly:
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res = context.ShuffleXor(srcA, srcB, srcC);
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break;
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}
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context.Copy(GetDest(context), res);
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}
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}
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} |