c26f3774bd
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes * Re-align opcode table * Re-enable undefined, use subclasses to fix checks * Add test and fix VRSHR instruction * PR feedback
81 lines
2.6 KiB
C#
81 lines
2.6 KiB
C#
#define SimdRegElem32
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using ARMeilleure.State;
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using NUnit.Framework;
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using System;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdRegElem32")]
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public sealed class CpuTestSimdRegElem32 : CpuTest32
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{
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#if SimdRegElem32
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private const int RndCnt = 2;
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[Test, Pairwise, Description("VMUL.<size> {<Vd>}, <Vn>, <Vm>[<index>]")]
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public void Vmul_1I([Values(1u, 0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(26u, 25u, 10u, 9u, 2u, 0u)] uint rm,
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[Values(1u, 2u)] uint size,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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[Values] bool q)
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{
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uint opcode = 0xf2900840u & ~(3u << 20); // VMUL.I16 D0, D0, D0[0]
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if (q)
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{
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opcode |= 1 << 24;
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rn <<= 1;
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rd <<= 1;
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}
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
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opcode |= size << 20;
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VMULL.<size> <Vd>, <Vn>, <Vm>[<index>]")]
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public void Vmull_1([Values(2u, 0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(26u, 25u, 10u, 9u, 2u, 0u)] uint rm,
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[Values(1u, 2u)] uint size,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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[Values] bool u)
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{
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uint opcode = 0xf2900a40u & ~(3u << 20); // VMULL.S16 Q0, D0, D0[0]
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
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opcode |= size << 20;
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if (u)
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{
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opcode |= 1 << 24;
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}
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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