mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-18 14:48:44 +02:00
212 lines
5.6 KiB
C#
212 lines
5.6 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System.Reflection.Emit;
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namespace ChocolArm64.Instruction
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{
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static class AInstEmitAluHelper
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{
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public static void EmitAdcsCCheck(AILEmitterCtx Context)
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{
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//C = (Rd == Rn && CIn) || Rd < Rn
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Context.EmitSttmp();
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Context.EmitLdtmp();
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Context.EmitLdtmp();
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EmitDataLoadRn(Context);
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Context.Emit(OpCodes.Ceq);
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Context.EmitLdflg((int)APState.CBit);
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Context.Emit(OpCodes.And);
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Context.EmitLdtmp();
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EmitDataLoadRn(Context);
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Context.Emit(OpCodes.Clt_Un);
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Context.Emit(OpCodes.Or);
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Context.EmitStflg((int)APState.CBit);
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}
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public static void EmitAddsCCheck(AILEmitterCtx Context)
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{
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//C = Rd < Rn
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Context.Emit(OpCodes.Dup);
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EmitDataLoadRn(Context);
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Context.Emit(OpCodes.Clt_Un);
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Context.EmitStflg((int)APState.CBit);
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}
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public static void EmitAddsVCheck(AILEmitterCtx Context)
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{
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//V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0
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Context.Emit(OpCodes.Dup);
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EmitDataLoadRn(Context);
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Context.Emit(OpCodes.Xor);
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.Xor);
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Context.Emit(OpCodes.Not);
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Context.Emit(OpCodes.And);
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Context.EmitLdc_I(0);
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Context.Emit(OpCodes.Clt);
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Context.EmitStflg((int)APState.VBit);
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}
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public static void EmitSbcsCCheck(AILEmitterCtx Context)
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{
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//C = (Rn == Rm && CIn) || Rn > Rm
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.Ceq);
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Context.EmitLdflg((int)APState.CBit);
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Context.Emit(OpCodes.And);
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.Cgt_Un);
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Context.Emit(OpCodes.Or);
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Context.EmitStflg((int)APState.CBit);
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}
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public static void EmitSubsCCheck(AILEmitterCtx Context)
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{
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//C = Rn == Rm || Rn > Rm = !(Rn < Rm)
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.Clt_Un);
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Context.EmitLdc_I4(1);
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Context.Emit(OpCodes.Xor);
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Context.EmitStflg((int)APState.CBit);
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}
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public static void EmitSubsVCheck(AILEmitterCtx Context)
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{
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//V = (Rd ^ Rn) & (Rn ^ Rm) < 0
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Context.Emit(OpCodes.Dup);
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EmitDataLoadRn(Context);
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Context.Emit(OpCodes.Xor);
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EmitDataLoadOpers(Context);
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Context.Emit(OpCodes.Xor);
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Context.Emit(OpCodes.And);
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Context.EmitLdc_I(0);
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Context.Emit(OpCodes.Clt);
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Context.EmitStflg((int)APState.VBit);
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}
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public static void EmitDataLoadRm(AILEmitterCtx Context)
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{
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Context.EmitLdintzr(((IAOpCodeAluRs)Context.CurrOp).Rm);
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}
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public static void EmitDataLoadOpers(AILEmitterCtx Context)
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{
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EmitDataLoadRn(Context);
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EmitDataLoadOper2(Context);
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}
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public static void EmitDataLoadRn(AILEmitterCtx Context)
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{
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IAOpCodeAlu Op = (IAOpCodeAlu)Context.CurrOp;
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if (Op.DataOp == ADataOp.Logical || Op is IAOpCodeAluRs)
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{
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Context.EmitLdintzr(Op.Rn);
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}
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else
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{
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Context.EmitLdint(Op.Rn);
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}
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}
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public static void EmitDataLoadOper2(AILEmitterCtx Context)
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{
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switch (Context.CurrOp)
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{
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case IAOpCodeAluImm Op:
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Context.EmitLdc_I(Op.Imm);
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break;
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case IAOpCodeAluRs Op:
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Context.EmitLdintzr(Op.Rm);
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switch (Op.ShiftType)
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{
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case AShiftType.Lsl: Context.EmitLsl(Op.Shift); break;
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case AShiftType.Lsr: Context.EmitLsr(Op.Shift); break;
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case AShiftType.Asr: Context.EmitAsr(Op.Shift); break;
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case AShiftType.Ror: Context.EmitRor(Op.Shift); break;
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}
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break;
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case IAOpCodeAluRx Op:
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Context.EmitLdintzr(Op.Rm);
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Context.EmitCast(Op.IntType);
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Context.EmitLsl(Op.Shift);
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break;
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}
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}
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public static void EmitDataStore(AILEmitterCtx Context) => EmitDataStore(Context, false);
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public static void EmitDataStoreS(AILEmitterCtx Context) => EmitDataStore(Context, true);
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public static void EmitDataStore(AILEmitterCtx Context, bool SetFlags)
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{
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IAOpCodeAlu Op = (IAOpCodeAlu)Context.CurrOp;
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if (SetFlags || Op is IAOpCodeAluRs)
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{
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Context.EmitStintzr(Op.Rd);
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}
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else
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{
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Context.EmitStint(Op.Rd);
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}
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}
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public static void EmitSetNZCV(AILEmitterCtx Context, int NZCV)
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{
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Context.EmitLdc_I4((NZCV >> 0) & 1);
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Context.EmitStflg((int)APState.VBit);
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Context.EmitLdc_I4((NZCV >> 1) & 1);
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Context.EmitStflg((int)APState.CBit);
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Context.EmitLdc_I4((NZCV >> 2) & 1);
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Context.EmitStflg((int)APState.ZBit);
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Context.EmitLdc_I4((NZCV >> 3) & 1);
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Context.EmitStflg((int)APState.NBit);
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}
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}
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} |