mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-18 06:38:42 +02:00
252 lines
6.4 KiB
C#
252 lines
6.4 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.Translation;
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using System.Reflection.Emit;
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using static ChocolArm64.Instruction.AInstEmitMemoryHelper;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void Adr(AILEmitterCtx Context)
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{
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AOpCodeAdr Op = (AOpCodeAdr)Context.CurrOp;
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Context.EmitLdc_I(Op.Position + Op.Imm);
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Context.EmitStintzr(Op.Rd);
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}
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public static void Adrp(AILEmitterCtx Context)
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{
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AOpCodeAdr Op = (AOpCodeAdr)Context.CurrOp;
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Context.EmitLdc_I((Op.Position & ~0xfffL) + (Op.Imm << 12));
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Context.EmitStintzr(Op.Rd);
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}
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public static void Ldr(AILEmitterCtx Context) => EmitLdr(Context, false);
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public static void Ldrs(AILEmitterCtx Context) => EmitLdr(Context, true);
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private static void EmitLdr(AILEmitterCtx Context, bool Signed)
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{
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AOpCodeMem Op = (AOpCodeMem)Context.CurrOp;
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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EmitLoadAddress(Context);
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if (Signed && Op.Extend64)
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{
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EmitReadSx64Call(Context, Op.Size);
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}
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else if (Signed)
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{
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EmitReadSx32Call(Context, Op.Size);
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}
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else
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{
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EmitReadZxCall(Context, Op.Size);
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}
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if (Op is IAOpCodeSimd)
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{
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Context.EmitStvec(Op.Rt);
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}
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else
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{
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Context.EmitStintzr(Op.Rt);
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}
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EmitWBackIfNeeded(Context);
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}
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public static void LdrLit(AILEmitterCtx Context)
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{
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IAOpCodeLit Op = (IAOpCodeLit)Context.CurrOp;
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if (Op.Prefetch)
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{
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return;
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}
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdc_I8(Op.Imm);
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if (Op.Signed)
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{
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EmitReadSx64Call(Context, Op.Size);
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}
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else
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{
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EmitReadZxCall(Context, Op.Size);
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}
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if (Op is IAOpCodeSimd)
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{
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Context.EmitStvec(Op.Rt);
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}
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else
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{
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Context.EmitStint(Op.Rt);
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}
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}
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public static void Ldp(AILEmitterCtx Context)
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{
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AOpCodeMemPair Op = (AOpCodeMemPair)Context.CurrOp;
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void EmitReadAndStore(int Rt)
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{
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if (Op.Extend64)
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{
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EmitReadSx64Call(Context, Op.Size);
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}
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else
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{
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EmitReadZxCall(Context, Op.Size);
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}
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if (Op is IAOpCodeSimd)
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{
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Context.EmitStvec(Rt);
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}
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else
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{
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Context.EmitStintzr(Rt);
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}
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}
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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EmitLoadAddress(Context);
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EmitReadAndStore(Op.Rt);
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdtmp();
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Context.EmitLdc_I8(1 << Op.Size);
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Context.Emit(OpCodes.Add);
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EmitReadAndStore(Op.Rt2);
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EmitWBackIfNeeded(Context);
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}
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public static void Str(AILEmitterCtx Context)
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{
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AOpCodeMem Op = (AOpCodeMem)Context.CurrOp;
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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EmitLoadAddress(Context);
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if (Op is IAOpCodeSimd)
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{
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Context.EmitLdvec(Op.Rt);
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}
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else
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{
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Context.EmitLdintzr(Op.Rt);
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}
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EmitWriteCall(Context, Op.Size);
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EmitWBackIfNeeded(Context);
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}
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public static void Stp(AILEmitterCtx Context)
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{
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AOpCodeMemPair Op = (AOpCodeMemPair)Context.CurrOp;
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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EmitLoadAddress(Context);
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if (Op is IAOpCodeSimd)
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{
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Context.EmitLdvec(Op.Rt);
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}
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else
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{
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Context.EmitLdintzr(Op.Rt);
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}
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EmitWriteCall(Context, Op.Size);
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdtmp();
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Context.EmitLdc_I8(1 << Op.Size);
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Context.Emit(OpCodes.Add);
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if (Op is IAOpCodeSimd)
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{
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Context.EmitLdvec(Op.Rt2);
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}
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else
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{
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Context.EmitLdintzr(Op.Rt2);
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}
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EmitWriteCall(Context, Op.Size);
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EmitWBackIfNeeded(Context);
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}
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private static void EmitLoadAddress(AILEmitterCtx Context)
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{
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switch (Context.CurrOp)
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{
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case AOpCodeMemImm Op:
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Context.EmitLdint(Op.Rn);
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if (!Op.PostIdx)
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{
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//Pre-indexing.
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Context.EmitLdc_I(Op.Imm);
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Context.Emit(OpCodes.Add);
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}
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break;
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case AOpCodeMemReg Op:
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Context.EmitLdint(Op.Rn);
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Context.EmitLdintzr(Op.Rm);
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Context.EmitCast(Op.IntType);
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if (Op.Shift)
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{
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Context.EmitLsl(Op.Size);
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}
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Context.Emit(OpCodes.Add);
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break;
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}
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//Save address to Scratch var since the register value may change.
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Context.Emit(OpCodes.Dup);
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Context.EmitSttmp();
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}
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private static void EmitWBackIfNeeded(AILEmitterCtx Context)
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{
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//Check whenever the current OpCode has post-indexed write back, if so write it.
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//Note: AOpCodeMemPair inherits from AOpCodeMemImm, so this works for both.
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if (Context.CurrOp is AOpCodeMemImm Op && Op.WBack)
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{
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Context.EmitLdtmp();
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if (Op.PostIdx)
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{
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Context.EmitLdc_I(Op.Imm);
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Context.Emit(OpCodes.Add);
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}
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Context.EmitStint(Op.Rn);
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}
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}
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}
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} |